SBIR Phase I: Ge-Free Strained Silicon Via dTCE Bonding (Differential Thermal Coefficient of Expansion Bonding)

本小型企业创新研究（SBIR）第一阶段提出将绝缘体上硅（SOI）制造技术与应变诱导晶片键合技术相结合，以生产应变绝缘体上硅（SSOI）晶片。 硅基器件， 硅/锗（Si/Ge）异质结构已经被广泛研究，并且这导致发现拉伸应变硅表现出上级电子特性。 双轴应变硅器件目前是通过昂贵的应变，这是一个高度技术性的异质结构制造工艺。 拉伸应变可以通过将硅假晶生长到较大晶胞的晶格（通常是Ge/Si的合金）上来引入。 在这项工作中，人们希望通过优化应变绝缘体上硅将载流子迁移率提高3倍以上，这项技术的预期好处将产生超快，主流的硅基电子产品，这将有效地成为新的主机材料，速度和性能将超过砷化镓（GaAs）。 数十亿美元的芯片行业将受益于降低新工厂设计技术的成本。

This Small Business Innovation Research (SBIR) Phase I propose to combine the technologies of silicon-on-insulator (SOI) manufacture with strain-inducing wafer bonding to produce Strained-Si On Insulator (SSOI) wafers. Silicon-based devices with silicon/germanium (Si/Ge) heterostructures have been extensively researched and this has lead to the discovery that tensile strained silicon exhibits superior electronic properties. Bi axially strained-silicon devices are currently strained via expensive which is a highly technical heterostructure fabrication process. Tensile strain can be introduced by growing silicon pseudomorphically on to a lattice of larger unit cell, usually an alloy of Ge/Si. In this work, it is hoped that by optimizing Strained-Silicon-on-Insulator will increase carrier mobilities by more than 3 times The anticipated benefits of this technology would yield ultra-fast, mainstream silicon-based electronics, which would effectively be new host materials with speed, and performance would surpass Gallium Arsenate (GaAs). The multi-billion dollar chips industry would benefit would benefit by reducing the costs for a new plant to design technology.