ITR WaveScalar: A New Approach to Scalable System Design
ITR WaveScalar: A New Approach to Scalable System Design
批准号:
0325635
负责人:
Mark Oskin
金额:
$129.99万
依托单位:
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2003
资助国家:
美国
项目状态:
已结题
起止时间:
2003-10-01 至 2009-05-31
中文摘要
摘要信息技术(IT)的迅速发展和普及是现代社会的核心。这是由于原始硅制造能力的指数增长使得计算能力迅速增加而成为可能。最近的研究表明,扩大我们目前的微处理器模型将不再把这些技术进步转化为性能的相应提高。WaveScalar是一种新的处理器架构,旨在扩展到下一个十年甚至更长时间。它通过将超大规模的大型慢速广播网络转换为短而快的点对点链路,直接面对新出现的线延迟问题。它是由易于设计的统一处理节点组成的网格构成的,其复杂性比当前的处理器设计低三个数量级。从这个提案中进行的研究将把这个新微处理器模型的架构、编译器和操作系统基础联系在一起。架构研究包括对WaveScalar系统架构的详细设计,包括节点设计、指令放置和系统互连的研究。编译器的研究包括开发针对WaveScalar的新优化技术,以及通过编译器支持来辅助微架构。操作系统组件包括对这个新计算平台中操作系统基本原语的研究,包括特定于应用程序的内存管理和上下文切换机制。最后,WaveScalar是一种低复杂度、高线程化的架构,因此可能非常适合纳米技术。将对这些新兴技术的WaveScalar架构进行详细的研究。
英文摘要
Wavescalar, A New Approach to Scalable System DesignAbstractAt the center of our modern society is the rapid growth and pervasiveness of Information Technology (IT). This has been made possible by the exponential increase in raw silicon fabrication capabilities enabling a rapid increase in computational power. Recent research has shown that scaling up our current microprocessor models will no longer convert these advances in technology to commensurate increases in performance. WaveScalar is a new processor architecture designed to scale into the next decade and beyond. It is designed to directly confront the emerging problems of wire delay by transforming the large slow broadcast networks of a superscalar into short fast point-to-point links. It is constructed from a grid of simple-to-design uniform processing nodes whose complexity is three orders of magnitude less than current processor designs.The research undertaken from this proposal will tie together the architecture, compiler, and operating system foundations of this new microprocessor model. The architecture research includes a detailed design of the architecture of the WaveScalar system, including investigation of node design, instruction placement, and system interconnects. The compiler research includes developing new optimization techniques specific to WaveScalar and assisting the microarchitecture through compiler support. The operating system component includes a study of basic primitives of operating systems in this new computing platform including mechanisms for application specific memory management and context switching. Finally, WaveScalar is a low-complexity, highly threaded architecture and as such may be well suited for nanotechnologies. A detailed investigation of the WaveScalar architecture for these emerging technologies will be undertaken.
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