CAREER: Soft Instruction Set Computing

随着每一代微处理器的相继问世，设计师们都在推动技术和复杂性的发展。但这些因素正在合谋使定制ASIC和代处理器的公认做法过时。设计、验证、掩模生成和测试等间接成本正在增长，将使继续采用当前策略变得令人望而却步。与此同时，人们越来越认识到，我们已经远远超过了提高单线程计算性能的收益递减点。未来将使我们转向无处不在的并行执行模型。最后，用户开始不仅要求性能，而且要求计算基础设施的可靠性和安全性。虽然最明显的基板是栅海FPGA，但它们的效率非常低，并且没有利用过去50年来进行的丰富的处理器研究。相反，我们提出了SISC，或软指令集计算。SISC处理器是一种通用处理器，没有固定的遗留指令集体系结构，也没有与周围系统环境的固定接口。然而，它确实利用了固定逻辑超标量处理器和细粒度FPGA的最佳特性，提供了一个高效、通用的计算基底，在此基础上进行实验并构建未来的安全、健壮和分布式系统。我们将通过展示SISC处理器提供现有传统指令集架构的有效仿真，提供流式数据流应用程序的峰值性能的平台，单，多线程和多处理器架构的统一，提供特定于应用程序的架构安全性的计算设备，高级语言的集成硬件支持和增强的本科生和研究生水平的计算机体系结构研究的灵活基板。这些应用目标将推动我们在设计真正通用的计算基板方面的研究。我们期望从这个职业生涯规划中获得以下成果：1。一个可配置的处理器设计，能够模拟最现代的指令集和一个平台，在其上构建新的安全应用程序架构.仿真工具、仿真技术和硬件原型的基础设施，以展示可重构处理基板的好处。自动编译算法和工具，用于SISC架构的运行时定制。一组安全的应用程序编译目标和操作系统技术，用于动态应用它们作为对网络攻击的响应。学生通过研究、学生讲习班和新课程接受有效系统设计和严格评价方法的培训。

With each successive generation of microprocessors designers push the envelopes of technology and complexity. But these factors are conspiring to make the accepted practice of custom ASICs, and generational processors obsolete. Overhead costs such as design, validation, mask-generation, and test are growing and will make it prohibitive to continue with the current strategies. Concurrent with this trend is the growing realization that we are well past the point of diminishing returns for enhancing single-threaded computational performance. The future will migrate us towards ubiquitous parallel models of execution. Finally, users are starting to demand not just performance but reliability and security from their computing infrastructure. While the obvious substrates are sea-of-gates FPGAs, they are highly inefficient and do not take advantage of the wealth of processor research conducted over the last 50 years. Instead, we propose SISC, or Soft-Instruction-Set-Computing. A SISC processor is a universal processor, with no fixed legacy instruction set architecture, and no fixed interface to the surrounding system envi-ronment. However, it does exploit the best features of both fixed-logic superscalar processors and fine-grained FPGAs to provide an efficient, generic, computing substrate on which to experiment and build the secure, robust and distributed systems of the future. We will demonstrate the capabilities of configurable substrates by showing that SISC processors provide efficient emulation of existing legacy instruction set architectures, a platform to provide peek performance on streaming data-flow applications, a unification of single, multi-threaded and multi-processor architectures, a computing device on which to provide application-specific architecture security, integrated hardware support for high-level languages and a flexible substrate for enhanced undergraduate and graduate level computer architecture research. These application goals will drive our research in the design of a truly universal computing substrate. We expect the following products from this career plan:1. A configurable processor design capable of emulating most modern instruction sets and a platform on which to construct new secure application architectures.2. An infrastructure of simulation tools, emulation techniques, and hardware prototypes to demonstrate the benefits of reconfigurable processing substrates.3. Automated compilation algorithms and tools for runtime customization of the SISC architecture.4. A set of secure application compilation targets and operating system techniques to dynamically apply them as a response to network attacks.5. Students trained in efficient system design and rigorous evaluation methodologies through research, student workshops and new courses.