High-Performance Stable Packet Switches

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National Science FoundationNETS - Research in Network Technologies and Systems CISE/CNSABSTRACTProposal Number: 0435303Principal Investigator: Panwar, Shivendra S.Institution: Polytechnic University of New YorkProposal Title: High-Performance Stable Packet SwitchesWhile switching capacity follows Moore's Law and doubles every 18 months, op-tical fiber line bandwidths double every 12 months. Consequently, packet switching technology continues to be one of the bottlenecks in the development of broadband networks. In this project, the research team has devised a new class of low complexity matching algorithms, i.e. Exhaustive Service Match with Hamiltonian Walk, which achieves stability and low packet delay, as opposed to cell delay, which was the focus of most previous research. Specifically, the fol-lowing two important issues are studied: (i) determination of the optimal packet delay for a matching algorithm, and (ii) options for the packet delay to increase sub-linearly with switch size under a general traffic pattern. This project will also address the class of switches that resolve the output contention by using the load balancing, where no scheduler is used, and re-sequencing is needed at the output. The total packet delay being investigated consists of the queuing delay and the re-sequencing delay. Another goal is to re-examine switch archi-tectures and their performance under more realistic long range dependent (LRD) traffic, and suggest improved architectures tuned to LRD traffic based on the insights thus derived.Dr. Admela JukanProgram Director, CISE/CNSAug 5, 2004.