CSR-EHS - Building a High Throughput Programmable Network Processor Through Algorithm and Architecture Co-Exploration

点击翻译按钮获取中文摘要

This project focuses on creating a programmable router processor designed to efficiently execute a variety of network algorithms with the goal to make it a feasible alternative to custom ASICs. To achieve the high throughput required by core routers, the research will focus on (1) fast data plane algorithms, (2) support for co-exploration of algorithms and architecture design, and (3) creating low power routers that do not sacrifice worst case throughput. The project will spur the development of more revolutionary approaches to high speed network processors, allowing programmable processors to penetrate the core router market. This in turn can help reduce the cost of building and maintaining routers. The results will also help reduce the power costs to run these high speed network routers. In terms of academic impact, this research will bring collaboration between two hitherto separate academic communities (computer architecture and networking) to spark new ideas from thisinterdisciplinary interaction.