Selective Way Activation of Set-Associativity Caches: Low-Power Design and Test

当今社会高度依赖于便携式数字设备，如手机、PDA、笔记本电脑、MP3播放器、数码相机/摄像机等。使用这些设备时，电池寿命是主要问题之一。高速缓存占整个CPU芯片动态和泄漏能量的很大一部分（30-60%），未来的计算机系统将使用更大的高速缓存，这将消耗更多的功率。因此降低快取系统的耗电量是一个重要的研究课题。通常使用集关联高速缓存，因为它们比直接映射高速缓存引起更少的未命中。另一方面，它们通常具有较慢的命中时间和较高的功耗，因为多个标签和数据库被并行探测。该项目的目标是检查地址亲和性和部分比较信息，可以用来减少操作缓存集的关联性，从而节省缓存访问能量，有时甚至访问延迟。两个新的高速缓存架构将被研究，以显着降低动态功耗的集相联高速缓存。其他研究课题包括新的故障模型，测试方法，和容错设计的高速缓存存储器，实现低泄漏功耗电路使用的昏昏欲睡的高速缓存技术。

Today's society highly depends on portable digital devices such as cell phones, PDAs, laptop computers, MP3 players, digital cameras/camcorders, etc. Battery life is one of the major concerns when using these devices. Caches have accounted for a significant fraction (30-60%) of the overall CPU chip dynamic and leakage energy, and tomorrow's computer systems will use even larger caches which will consume more power. Thus lowering the power-consumption of a cache system is an important research topic. Set-associative caches are commonly used because they incur fewer misses than direct-mapped caches. One the other hand, they typically have slower hit times and higher power consumption, because multiple tag and data banks are probed in parallel. The goal of this project is to examine address affinity and partial comparison information which can be used to reduce operational cache set-associativity, thus save cache access energy and some times even access latency. Two new cache architectures will be studied to significantly reduce the dynamic power consumptions for set-associative caches. Other research topics include new fault models, test methods, and fault-tolerant designs for cache memories that implement low-leakage power dissipation circuits using the drowsy cache technique.