Asynchronous Circuits and Systems for Nanoelectronics

纳米电子学异步电路和系统

• 批准号: 0541461
• 负责人: Alain Martin
• 金额: $ 110万
• 依托单位: California Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-08-15 至 2010-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541461&HistoricalAwards=false
• 关键词: Asynchronous; Circuits; Systems; Nanoelectronics

Prop ID: CCF-0541461 PI: Martin, Alain J. Institution: California Institute of Technology Title: Asynchronous Circuits and Systems for Nanoelectronics It is expected that CMOS, today's technology of choice for semiconductor-based integrated circuits, will soon run into fundamental physical limits mainly due to the lithographic process used to pattern the circuits. Among all possible successors, non-lithographic molecular-electronic technology based on carbon nanotubes and nanowires is one of the most promising. Because of inherent fabrication difficulties, circuits in those technologies will exhibit large variations in physical parameters as well as large percentage of faults and defects. Taking parameter variability and defect- and fault-tolerance into account will be an inherent part of any successful circuit design methodology in the nanoscale era. Because any variation in an electrical parameter has an effect on the timing behavior of the circuit, being able to design a circuit in a manner such that the correct behavior of the circuit is independent of the timing is a great advantage since it would greatly increase the robustness of the circuit to parameter variations. Such a design style is called ``asynchronous''. The purpose of this research is to develop a design method for molecular-electronic integrated circuits based on asynchronous logic, including error- and defect-tolerance circuit techniques. Another reason for using asynchronous logic is that such logic does not need a clock to implement the sequencing of actions in a typical digital system like a microprocessor. Distributing a clock signal across a chip requires long wires with well-balanced timing properties, which is impossible to do in molecular electronic.The research will develop design methods to deal with both hard defects like broken wires, and soft (or transient) errors as caused for instance by an alpha particle hitting the circuit and changing a bit from zero to one. Dealing with hard errors will require redundancy to be able to use ``spares'' and reconfigurability to redesign a circuit on the fly to circumvent an error. For all those unpredictable changes in the circuit, independence of timing offered by asynchrony will be a great advantage.Because of the non-lithographic nature of the fabrication process, molecular electronics restricts the geometry of the chips. Essentially, a wire can run either north-south or east-west, and all active devices (transistors) are built at the intersection between a north-south wire and an east-west one.This restricted geometry calls for large regular structures like FPGAs, rather than random logic with arbitrary geometry. Designing within this restricted geometry (with the additional issue of very highly resistive contacts between wires of different direction) is another challenge of this project.The project will propose and test a complete asynchronous logic family for molecular electronic devices based on carbone nanotubes and nanowires and a design method to deal with different aspects of fault- and defect-tolerance. It is hoped that a significant chip, for instance a small microcontroller, will be designed and fabricated.

道具ID：CCF-0541461 PI：Martin，Alain J.机构：加州理工学院标题：纳米电子学异步电路和系统 预计CMOS，今天的选择为基于半导体的集成电路的技术，将很快遇到基本的物理限制，主要是由于用于图案化电路的光刻工艺。在所有可能的继任者中，基于碳纳米管和纳米线的非光刻分子电子技术是最有前途的技术之一。由于固有的制造困难，这些技术中的电路将表现出物理参数的大变化以及大百分比的故障和缺陷。考虑到参数的可变性和缺陷和容错将是一个固有的部分，任何成功的电路设计方法在纳米时代。由于电气参数的任何变化都会影响电路的定时行为，因此能够以电路的正确行为独立于定时的方式设计电路是一个很大的优势，因为这将大大增加电路的鲁棒性参数变化。这样的设计风格被称为“风格”。本研究的目的是发展一种基于异步逻辑的分子电子集成电路的设计方法，包括容错和容错电路技术。使用异步逻辑的另一个原因是这种逻辑不需要时钟来实现典型数字系统（如微处理器）中的动作序列。在芯片上分配时钟信号需要具有良好平衡定时特性的长导线，这在分子电子学中是不可能做到的。这项研究将开发设计方法，以处理诸如断线等硬缺陷和诸如阿尔法粒子击中电路并从0变为1的位所引起的软（或瞬态）错误。处理硬错误将需要冗余，以便能够使用“备件”和可重新配置性，以便在运行中重新设计电路来规避错误。对于电路中的所有这些不可预测的变化，分子电子学提供的时序独立性将是一个很大的优势。由于制造过程的非光刻性质，分子电子学限制了芯片的几何形状。从本质上讲，一条线可以是南北走向，也可以是东西走向，所有的有源器件（晶体管）都建在南北线和东西线的交叉点上。这种受限的几何结构要求像FPGA这样的大型规则结构，而不是具有任意几何形状的随机逻辑。该项目的另一个挑战是在这种受限的几何结构中进行设计（不同方向的导线之间存在非常高的电阻接触）。该项目将提出并测试基于碳纳米管和纳米线的分子电子器件的完整异步逻辑系列，以及处理容错和缺陷容限的不同方面的设计方法。希望设计和制造一个重要的芯片，例如一个小型微控制器。