NGS: A Design Environment for Single Chip Heterogeneous Multiprocessors

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Within the next five years, it will be possible to provide enough transistors on a single chip for on the order of a hundred ARM-equivalent processors. At that point, individual, programmable processors will be like registers were to early VLSI design - building blocks within a larger organizing framework. The investigators refer to this class of devices as Programmable Heterogeneous Multiprocessors (PHMs), emphasizing that not only will individual processors on the chip be programmable, but collections of processors on the chip as well as the chip as a whole must be considered programmable. Applications that might appear on such devices include that of current cell phones, current personal digital assistant (PDA) applications, global positioning system (GPS) sensing, Bluetooth, motion sensing, ad hoc networking, 3-D image processing,compression/decompression, security, multimedia and a broad set of human computer interaction(HCI) software. Ubiquitous and pervasive computing will produce newer scenarios with even more complex functionality. But these possibilities are limited by the ability to design and technically realize these scenarios in the individual space and power-constrained computing devices. The class of single-chip computing that will leave the desktop in meeting the needs of future computing poses distinctly different programming and design challenges from board and network-level heterogeneous multiprocessors because a single chip is a finite resource, the hardware design will be semi-custom, and coordination of system resources will be required. All of these speak to levels of optimization that will be required for consumer electronic devices because of their physical limitations.The project will investigate new design strategies that leverage the next level of design that is enabled as system performance can be evaluated with reduced modeling detail. The approach will define novel views of the proposed functionality and multiprocessor architecture, enabling simulation and optimization of the whole system's performance. Novel, proposed strategies include the development of design scenarios, which are the answer to the currently separate views of testbenches that exercise computer systems and benchmarks that are used to evaluate programmable designs, and the enabling of novel system-level strategies to save power by using a larger number of simpler processors that execute at lower clock rates or with sophisticated multiprocessor-level scheduling strategies. While ambitious, the project's vision isenabled because of prior work in developing a novel simulator that capture the performance interactions of concurrent software executing on concurrent hardware using a layered model.