Memory Caching and Prefetching to Improve I/O Performance in High-End Systems

随着处理器和网络技术的快速发展，随着内存和磁盘价格的下降，CPU周期的计算资源、内外连接(内存、I/O和Internet)不同级别的可用带宽以及大容量的内存和磁盘对我们构建高端系统来说越来越充足。遗憾的是，数据访问时延的改善，特别是对磁盘的访问时延的改善明显滞后。CPU上的数据处理和磁盘上的数据访问之间的速度差距已经达到了无法忍受的程度，而且只会随着时间的推移而变得更糟。这一瓶颈严重阻碍了针对需要快速访问海量数据的数据密集型应用的高端计算系统的发展。解决这一问题的一种方法是利用DRAM存储器的低价格和大容量建立大容量的内存缓冲区来缓存数据以供重复使用，并利用网络的高带宽和空闲带宽预取数据以供预测使用。本研究项目将集中在一个小缓冲区缓存主题上：开发并测试一个通用的基于时钟的系统框架，用于核心、分布式和Internet系统的大范围存储层次结构中的缓存管理。PI将设计和实现一个基于时钟的统一的内存缓冲区管理框架，具有以下独特的优点：(1)它不需要任何全局同步，并且它是独立于系统的；(2)它可以方便地用于存储层次结构中任何级别的缓冲区管理，例如用于I/O数据的缓冲区缓存、用于大型科学数据库的数据缓冲区、用于大型数据流的内存缓冲区等；以及(3)它将被设计为灵活地采用和测试不同类型的利用数据访问局部的新想法。

With the rapid advancement of processor and networking technology, and with the falling price of memory and disks, computing resources of CPU cycles, available bandwidths at different levels of inter- and external connections (memory, I/O, and Internet), and large capacity of memory and disks are increasingly plentiful to us to build high-end systems. Unfortunately, the improvement of data access latency, particularly, the access latency to disks, has significantly lagged behind. The speed gap between data processing in CPU and data accessing in disks has reached to an intolerable level and will only become worse as time goes by. This bottleneck has seriously hindered the development of high-end computing systems for data-intensive applications that demand fast accesses to a huge amount of data. One solution to address this problem is to build large memory buffers to cache data for reuse by taking advantage of low price and large capacity of DRAM memory, and to prefetch data for predicted future use by taking advantage of high and idle bandwidths of networks.This research project will focus on a small buffer caching topic: to develop and test a general clock-based system framework for caching management in a large scope of storage hierarchy for core, distributed and Internet systems. The PI will design and implement a clock-based and unified memory buffer management framework with following unique merits: (1) it does not require any global synchronization, and it is system independent; (2) it will be easily used by any types of buffer management at any level of the storage hierarchy, such as buffer caches for I/O data, data buffer for large scientific data bases, memory buffers for large data streams, and others; and (3) it will be designed to flexibly adopt and test different types of novel ideas of exploiting data access localities.