CT-ER: Augmenting Branch Prediction for Trusted Computing

CT-ER：增强可信计算的分支预测提案编号：0627341 PI：Gyungho Lee，伊利诺伊大学芝加哥分校摘要：在当前的处理器架构中，在机器指令级的控制流跟踪是盲目的，没有有效性检查。无论程序计数器指向什么指令，都会被取出并执行。每当这种盲目的指令排序没有被系统和应用程序软件在更高级别上正确解决时，它就成为恶意软件利用的漏洞。为了弥补这一根本缺陷，本项目探索将控制流验证纳入现代高性能流水线处理器。控制流验证的一个简单的想法是收集每个分支的可能目标地址，以检查每个分支实例。现代微处理器在某种意义上已经在微体系结构级别以分支预测的形式进行这种检查。由于程序执行中的非法控制转移只能在处理器的程序计数器被“强制”指向“看不见的”地址时进行，因此控制流改变攻击在处理器微体系结构中引起分支误预测;分支误预测是程序执行中的不当行为（诸如二进制代码篡改和病毒感染）的症状之一。本计画发展一种微架构，将控制流验证纳入现代高效能管线处理器的分支预测单元。具有安全控制流的处理器内核为设计和构建更可信的设备和网络基础设施奠定了基础。该项目将为验证程序控制流提供实用的硬件支持，以防止未知的攻击和漏洞利用，即在分析和捕获行为模式，攻击签名或漏洞利用之前。

CT-ER: Augmenting Branch Prediction for Trusted ComputingProposal No.: 0627341PI: Gyungho Lee, University of Illinois at ChicagoAbstract:Control flow tracking at the machine instruction level is blindfolded without a validity check in the current processor architecture. Whatever the program counter points to the instruction is fetched and executed. Whenever this blindfolded instruction sequencing is not properly addressed at a higher level by system and application software, it becomes a vulnerability that malicious software exploits. To mend this fundamental flaw, this project explores incorporating control flow validation into modern high-performance pipelined processors. A straightforward idea of control flow validation can be collecting possible target addresses per branch to check every branching instance. Modern microprocessors do this checking in some sense already at micro-architecture level in the form of branch prediction. Since illegitimate control transfer in program execution can be made only when the processor's program counter is "forced" to point to "unseen" addresses, control flow altering attacks cause branch mis-predictions in the processor micro-architecture; branch mis-prediction is one of the symptoms of misbehavior in program execution such as binary code tampering and virus infection. This project develops micro-architecture for incorporating control flow validation into the branch prediction unit of modern high-performance pipelined processors. A processor core with secure control flow creates a basis for designing and building more trusted devices and cyber infrastructure. This project will produce a practical hardware support for validating program control flow to provide protection from not-yet-known attacks and exploits, i.e. before the behavior patterns, attack signatures, or vulnerabilities they exploit are analyzed and captured.