High-Bandwidth Memory Pipeline for Wide-Issue Processors

摘要：技术和架构上的创新使得功能强大的微处理器能够以非常高的时钟速率同时发出多条指令。在未来具有积极推测技术的处理器中，每个周期的指令问题数量预计会更大。有效地处理内存引用以进行数据访问是实现未来处理器高性能的关键之一。本研究解决了在每个周期发出数十条指令的宽问题处理器中为数据访问提供快速延迟的足够带宽的方法。这些方法基于“数据解耦”的概念。数据解耦将内存引用指令在它们访问的数据的实际地址已知之前划分为多个独立的流。然后将分区内存引用指令送入单独的内存管道。本研究探讨了基于数据解耦的多存储管道的有效和高效的硬件和软件支持问题。与传统设计相比，提供多个内存管道的数据解耦方法可以提供两个关键优势。首先，降低了构建具有许多端口的大型缓存的成本和复杂性。其次，分区内存引用可以促进对每个分区流的更专门化处理。

ABSTRACTProposal: 0073259PI: Gyungho LeeTitle: High-Bandwidth Memory Pipeline for Wide-Issue Processors Technological and architectural innovations have enabled development of powerful microprocessors that can issue several instructions concurrently at a very high clock rate. In future processors with aggressive speculation techniques, an even larger number of instruction issues per cycle are expected. Efficient handling of memory references for data access is one of the keys to achieving high performance in future processors. This research addresses methods to provide sufficient bandwidth at fast latency for data access in wide-issue processors issuing tens of instructions per cycle. The methods are based on the concept of "data decoupling". Data decoupling divides the memory reference instructions into multiple independent streams before the actual addresses of the data they access are known. Partitioned memory reference instructions are then fed into a separate memory pipeline. This research investigates the issues in effective and efficient hardware and software support for multiple memory pipelines based on data decoupling. The data decoupling approach of providing multiple memory pipelines can provide two crucial advantages over a conventional design. First, the cost and the complexity of building a large cache with many ports are reduced. Second, partitioning memory references can facilitate more specialized handling of each partitioned stream.