SBIR Phase I: VLSI Clocking Using BDS Technology
SBIR Phase I: VLSI Clocking Using BDS Technology
批准号:
0711680
负责人:
Mihai Banu
金额:
$10.0万
依托单位:
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2007
资助国家:
美国
项目状态:
已结题
起止时间:
2007-07-01 至 2007-12-31
中文摘要
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英文摘要
This Small Business Innovation Research (SBIR) Phase I research project will validate the Bi-Directional Signaling (BDS) concept in Very Large Scale Integrated Circuits (VLSI) clock distribution applications. The BDS concept was introduced recently as an idea enabling a disruptive new technology for VLSI clocking with significant implications in the VLSI design methodology. Similar to other recent research ideas, BDS replaces the dissipative and noisy signal transport inherent in conventional active trees with electromagnetic wave propagation, accomplishing major reductions in power dissipation, jitter, and travel time. BDS is a wide-band, openloop (driven) system naturally supporting fast clock start/stop operations and a very wide range of clock frequencies. In addition, unlike any other VLSI clocking techniques, BDS decouples the signal transport function from the local-area loading effects for almost complete freedom in clock distribution routing. If the theoretical promises of BDS turn into reality and the VLSI chip manufactures adopt this technology, the significant benefits will include faster IC development cycles, lower IC cost, higher yields, and better performance.
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SBIR Phase II: VLSI Clocking Using BDS Technology
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批准号:0822830
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项目类别:Standard Grant
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资助金额:$0.0万
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财政年份:2008
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负责人:Mihai Banu
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依托单位:
STTR Phase I: RF-System and Integrated Electronics for Low-Cost Smart Antenna Arrays
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批准号:0810423
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项目类别:Standard Grant
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资助金额:$15.0万
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财政年份:2008
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负责人:Mihai Banu
-
依托单位:
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