Collaborative Research: CSR---CORE---EHS: PRET: Precision Timed Architectures

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Abstractions currently used in computing hide timing properties of software. As a consequence, computer scientists have developed techniques that deliver improved average-case performance and/or design convenience at the expense of timing predictability. For embedded software, which interacts closely with physical processes, timing is usually an essential property. Lack of timing in the core abstractions results in brittle and non-portable designs. Moreover, as embedded software becomes more networked, the prevailing empirical test-based approach to achieving real-time computing becomes inadequate.This project reintroduces timing predictability as a first-class property of embedded processor architectures. It tackles the problem from the hardware design perspective, developing precision timed (PRET) machines as soft cores on FPGAs. It shows that software on PRET machines can be integrated with what would traditionally have been purely hardware designs. This project seeks to reinvigorate research in an area of computer science and computer architecure that have stagnated in research due to maturing industrial practice. This is expected to provide a starting point for a decades-long revolution that will once again make timing predictability an essential feature of processors. This project addresses the core abstractions of computing. Rather than attempting to correct the lack of timing in these abstractions with more layers of abstraction, this project has the goal of showing that embedded processors can deliver both predictable timing and high performance. It opens up the field to new computing abstractions that include timing as a first-class property.