SHF: Medium: Compiling Parallel Algorithms to Memory Systems

SHF：中：将并行算法编译到内存系统

• 批准号: 1162124
• 负责人: Stephen Edwards
• 金额: $ 119.99万
• 依托单位: Columbia University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-04-01 至 2019-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1162124&HistoricalAwards=false
• 关键词: SHF; Medium; Compiling; Parallel; Algorithms

This project aims to improve the practice of parallel programming - perhaps the central problem facing computer science in the 21st century. While the sequential model first introduced by Von Neumann and others has served us well, its inefficiency has been brought into sharp focus by the availability of billion-transistor chips, which are greatly underutilized yet power-hungry when running sequential algorithms.This project aims to improve the programmability and efficiency of distributed memory systems, a key issue in the execution of parallel algorithms. While it is fairly easy to put, say, thousands of independent adders on a single chip, it is far more difficult to supply them with useful data to add, a task that falls to the memory system. This research will develop compiler optimization algorithms able to configure and orchestrate parallel memory systems able to utilize such parallel computational resources.To make more than incremental progress, this project departs from existing hegemony in two important ways. First, its techniques will be applied only to algorithms expressed in the functional style, a more abstract, mathematically sound representation that enables precise reasoning about parallel algorithms and very aggressive optimizations. Second, it targets field-programmable gate arrays (FPGAs) rather than existing parallel computing platforms. FPGAs provide a highly flexible platform that enables exploring parallel architectures far different than today's awkward solutions, which are largely legacy sequential architectures glued together. While FPGAs are far too flexible and power-hungry to be the long-term "solution"to the parallel computer architecture question, their use grounds this project in physical reality and will produce useful hardware synthesis algorithms as a side-effect.Judicious and efficient data movement is the linchpin of parallel computing. This project attacks that challenge head on, establishing the constructs and algorithms necessary for hardware and software to efficiently manipulate data together. This research will lay the groundwork for the next generation of storage and instruction set architectures, compilers, and programming paradigms -- the bedrock of today's mainstream computing.

这个项目旨在提高并行编程的实践--这也许是21世纪世纪计算机科学面临的中心问题。 虽然冯·诺依曼等人首先提出的顺序模型为我们提供了很好的服务，但其低效率已经成为人们关注的焦点，因为数十亿晶体管芯片的可用性，这些芯片在运行顺序算法时大大未得到充分利用，而且功耗很大。本项目旨在提高分布式存储系统的可编程性和效率，这是并行算法执行的关键问题。 虽然在一个芯片上放置数千个独立的加法器相当容易，但要为它们提供有用的数据来添加就困难得多了，这一任务福尔斯在了存储系统上。 这项研究将开发编译器优化算法能够配置和编排并行内存系统能够利用这种并行计算resources.To使更多的增量进展，这个项目从现有的霸权在两个重要的方面。 首先，它的技术将只应用于以函数式风格表达的算法，这是一种更抽象、数学上合理的表示，可以对并行算法进行精确推理，并进行非常积极的优化。 其次，它的目标是现场可编程门阵列（FPGA），而不是现有的并行计算平台。 FPGA提供了一个高度灵活的平台，可以探索与当今笨拙的解决方案截然不同的并行架构，这些解决方案在很大程度上是传统的顺序架构粘在一起。 虽然FPGA过于灵活和耗电，无法成为并行计算机体系结构问题的长期“解决方案“，但它们的使用使该项目在物理现实中得以实现，并将产生有用的硬件综合算法作为副作用。 这个项目的攻击，挑战迎面而来，建立必要的硬件和软件的结构和算法，以有效地操纵数据在一起。 这项研究将为下一代存储和指令集体系结构、编译器和编程范式奠定基础，这些都是当今主流计算的基石。