Collaborative Research: CSR-EHS: Pret: Precision Timed Architectures

协作研究：CSR-EHS：Pret：精确定时架构

• 批准号: 0720882
• 负责人: Edward Lee
• 金额: $ 55万
• 依托单位: University of California-Berkeley
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-08-01 至 2013-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0720882&HistoricalAwards=false
• 关键词: Collaborative; Research; CSR; EHS; Pret

Abstractions currently used in computing hide timing properties of software. As a consequence, computer scientists have developed techniques that deliver improved average-case performance and/or design convenience at the expense of timing predictability. For embedded software, which interacts closely with physical processes, timing is usually an essential property. Lack of timing in the core abstractions results in brittle and non-portable designs. Moreover, as embedded software becomes more networked, the prevailing empirical test-based approach to achieving real-time computing becomes inadequate.This project reintroduces timing predictability as a first-class property of embedded processor architectures. It tackles the problem from the hardware design perspective, developing precision timed (PRET) machines as soft cores on FPGAs. It shows that software on PRET machines can be integrated with what would traditionally have been purely hardware designs. This project seeks to reinvigorate research in an area of computer science and computer architecure that have stagnated in research due to maturing industrial practice. This is expected to provide a starting point for a decades-long revolution that will once again make timing predictability an essential feature of processors. This project addresses the core abstractions of computing. Rather than attempting to correct the lack of timing in these abstractions with more layers of abstraction, this project has the goal of showing that embedded processors can deliver both predictable timing and high performance. It opens up the field to new computing abstractions that include timing as a first-class property.

目前用于计算的抽象隐藏了软件的时间属性。因此，计算机科学家已经开发出技术，以牺牲时序可预测性为代价来提供改进的平均情况性能和/或设计便利性。对于与物理过程密切交互的嵌入式软件，时序通常是一个基本属性。在核心抽象中缺乏时序会导致脆弱和不可移植的设计。此外，随着嵌入式软件变得更加网络化，目前流行的经验测试为基础的方法来实现实时计算变得insufficient.This项目重新引入时序的可预测性作为嵌入式处理器架构的一流属性。它从硬件设计的角度来解决这个问题，开发精密定时（PRET）机器作为FPGA上的软核。它表明，PRET机器上的软件可以与传统上纯粹的硬件设计相集成。该项目旨在重振计算机科学和计算机体系结构领域的研究，这些领域的研究由于成熟的工业实践而停滞不前。预计这将为一场长达数十年的革命提供一个起点，这场革命将再次使时序可预测性成为处理器的一个基本特征。 该项目解决了计算的核心抽象问题。这个项目的目标不是试图用更多的抽象层来纠正这些抽象中缺乏时序的问题，而是表明嵌入式处理器可以提供可预测的时序和高性能。它开辟了新的计算抽象领域，包括计时作为一个一流的属性。