Collaborative Research: CSR-PSCE, SM: Memory Thermal Management for Multi-Core Systems

随着多核处理器对内存性能要求的不断提高，内存子系统与处理器和硬盘驱动器一起成为新的热点问题。为了解决这一新出现的问题，该项目解决了几个新的系统级动态热管理(DTM)方案，这些方案将DRAM热管理与处理器性能节流相协调，例如动态调整活动处理器核心的数量或基于内存热状态调整处理器的频率和电压水平。该项目还研究了协调的热管理方案，该方案考虑了处理器和存储器子系统的热需求。通过适当地混合具有不同内存需求的作业，进一步考虑了热感知操作系统作业调度，以随着时间的推移平滑内存流量和DRAM热产生。此外，考虑到每个芯片的位置和每个应用程序的存储器访问需求，提出了热感知页面分配，以避免某些存储芯片的不平衡过热。这些方案将首先通过模拟进行评估，然后在操作系统内核中实现，并在真实系统上进行评估。为了支持存储器热研究，提出了一种简单而准确的热模型来估计DRAM存储子系统的动态温度变化。将开发一个两级模拟器来模拟存储子系统的热行为。成功地解决存储子系统的散热问题，不仅可以保证系统的安全运行，还可以提高系统的整体性能，降低系统制造成本，提高系统的电源效率。

With the increasing demand on memory performance by multi-core processors, the memory subsystem has become a new thermal concern along with the processor and the hard disk drive. To address this emerging issue, this project addresses several new, system-level Dynamic Thermal Management (DTM) schemes that coordinate the DRAM thermal management with the processor performance throttling, such as dynamically adjusting the number of active processor cores or scaling the processor's frequency and voltage level based on the memory thermal status. The project also studies coordinated thermal management schemes that consider the thermal requirements from both the processor and the memory subsystem. Thermal-aware OS job scheduling is further considered to smooth memory traffic and DRAM heat generation over time by mixing jobs with different memory demands appropriately. In addition, thermal-aware page allocation is proposed to avoid unbalanced overheating from some memory chips by considering the location of each chip and the memory access demand of each application. These schemes will first be evaluated using simulation and then implemented in OS kernels and evaluated on real systems. To support the memory thermal studies, a simple and accurate thermal model is proposed to estimate the dynamic temperature changes of DRAM memory subsystems. A two-level simulator will be developed to emulate the thermal behavior of memory subsystems. Successfully addressing the thermal concern of memory subsystems will not only ensure safe system operations but also improve the overall system performance, reduce the system manufacturing cost, and improve the system power efficiency.