Collaborative Research: CSR-PSCE, SM: Memory Thermal Management for Multi-Core Systems

随着多核处理器对存储器性能的需求不断增加，存储器子系统已经成为与处理器和硬盘驱动器一起沿着的新的热问题。为了解决这一新出现的问题，该项目提出了几种新的系统级动态热管理（DTM）方案，这些方案将DRAM热管理与处理器性能调节相协调，例如动态调整活动处理器内核的数量或根据内存热状态调整处理器的频率和电压水平。该项目还研究了协调的热管理方案，考虑处理器和存储器子系统的热要求。热感知OS作业调度被进一步考虑，以通过适当地混合具有不同存储器需求的作业来平滑存储器流量和DRAM热生成。此外，热感知页面分配提出，以避免不平衡的过热，从一些存储器芯片，通过考虑每个芯片的位置和每个应用程序的存储器访问需求。这些方案将首先使用模拟进行评估，然后在OS内核中实现，并在真实的系统上进行评估。为了支持存储器热研究，提出了一个简单而准确的热模型来估计动态温度变化的DRAM存储器子系统。将开发一个两级模拟器来模拟存储器子系统的热行为。成功解决存储器子系统的热问题不仅可以确保系统安全运行，而且可以提高系统的整体性能，降低系统制造成本，并提高系统的功率效率。

With the increasing demand on memory performance by multi-core processors, the memory subsystem has become a new thermal concern along with the processor and the hard disk drive. To address this emerging issue, this project addresses several new, system-level Dynamic Thermal Management (DTM) schemes that coordinate the DRAM thermal management with the processor performance throttling, such as dynamically adjusting the number of active processor cores or scaling the processor's frequency and voltage level based on the memory thermal status. The project also studies coordinated thermal management schemes that consider the thermal requirements from both the processor and the memory subsystem. Thermal-aware OS job scheduling is further considered to smooth memory traffic and DRAM heat generation over time by mixing jobs with different memory demands appropriately. In addition, thermal-aware page allocation is proposed to avoid unbalanced overheating from some memory chips by considering the location of each chip and the memory access demand of each application. These schemes will first be evaluated using simulation and then implemented in OS kernels and evaluated on real systems. To support the memory thermal studies, a simple and accurate thermal model is proposed to estimate the dynamic temperature changes of DRAM memory subsystems. A two-level simulator will be developed to emulate the thermal behavior of memory subsystems. Successfully addressing the thermal concern of memory subsystems will not only ensure safe system operations but also improve the overall system performance, reduce the system manufacturing cost, and improve the system power efficiency.