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SHF: EAGER: Closing the gap in Controller Synthesis

SHF: EAGER: Closing the gap in Controller Synthesis
SHF:EAGER:缩小控制器合成方面的差距
批准号:
0953994
负责人:
Rupak Majumdar
金额:
$20.0万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2009
资助国家:
美国
项目状态:
已结题
起止时间:
2009-09-01 至 2012-08-31

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中文摘要
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英文摘要
Automatic controller synthesis algorithms hold the promise of producing correct-by-construction systems, obviating the need for costly post facto verification. However, there is currently a gap between theoretical foundations of controller synthesis and their practical implementations on hardware and software platforms. This project addresses challenges in closing the gap in control synthesis. In particular, we consider two fundamental problems. First, we consider the problem of implementation complexity of controllers. While theoretical results have focused on the optimal memory requirements for controllers, in practice, a controller implementation may have several other optimality requirements such as the size of the implementing (combinational and sequential) circuit, the complexity and frequency of computing the control action, and the sensing and actuation bandwidth. Accordingly, we study algorithms for the construction of optimal controllers under these metrics. Second, we consider the problem of fault tolerance in controllers, in which we consider effects of (possibly stochastic) errors in controller implementations. While traditional fault tolerance techniques such as error-correcting codes and redundancy can be applied directly, our thesis is that a closer interaction of fault tolerance with controller synthesis algorithms can lead to fault tolerant designs at costs lower than traditional techniques. For example, by distinguishing the "importance" of signals to the control objective, the costs associated with error-correction and redundancy can be decreased while having a negligible effect on the control objective. The research performed in this project is prerequisite for a more widespread adoption of correct-by-construction techniques.The tools and techniques developed in this project have the potential to significantly enhance our ability to produce robust cyber-physical systems, thus affecting several large-scale application areas beyond the computer science and control engineering domains. Practically, the results of the research will lead to better controller synthesis tools. Theoretically, the research will bring together cross-cutting techniques, ranging from theoretical foundations in logics and algorithms for control, to optimization techniques, real-time systems, and hardware and software synthesis. In addition, by fostering collaboration between software foundations, control foundations, and hardware synthesis foundations, the project will train graduate and undergraduate students in the emerging and important domain of formal techniques for cyber-physical systems.
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CSR---EHS: Collaborative: Directed Real-Time Testing
  • 批准号:
    0720881
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $22.5万
  • 财政年份:
    2007
  • 负责人:
    Rupak Majumdar
  • 依托单位:
Collaborative: Software Verification for Hardware Models
  • 批准号:
    0702743
  • 项目类别:
    Standard Grant
  • 资助金额:
    $25.0万
  • 财政年份:
    2007
  • 负责人:
    Rupak Majumdar
  • 依托单位:
CAREER: Modular Verification of Software
  • 批准号:
    0546170
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $32.0万
  • 财政年份:
    2006
  • 负责人:
    Rupak Majumdar
  • 依托单位:
海外基金