CAREER: Communication System Design for Future Integrated Circuits

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Over the next decade, advances in integrated circuit (IC) communication systems will encounter a number of interdependent challenges from system and architecture design to physical technology integration. With increasing system integration and technology scaling, the performance and scalability of electrical interconnect have become the primary bottleneck in IC design. Power and process variation induced thermal and reliability challenges further complicate IC communication system design and run-time operation. Looking forward, emerging system and physical technologies will vastly change the landscape of IC communication -- the move towards many-core systems and parallel applications increases the communication requirements and calls for new communication solutions to support system-level performance and functionality. Meanwhile, emerging physical technologies, such as nanophotonic interconnect and three-dimensional (3D) integration, are gradually becoming commercially feasible. Their adoption will offer new opportunities but also pose new challenges to IC communication system design.The research objective of this CAREER development plan is to systematically investigate communication system design for future ICs and address the corresponding research challenges from system exploration, modeling and analysis, to technology integration, emphasizing a unified study of emerging communication system and physical technologies. More specifically, it will focus on addressing the following two system-level and physical challenges: (1)How emerging many-core systems will change the communication system design; and (2) How emerging physical technologies will change the communication system design. This work aims to discover scientific knowledge necessary for a unified exploration of IC communication system design, and deliver new communication architectures and physical solutions, modeling and analysis methods, design methodologies, and optimization techniques. The end results will be demonstrated and validated with chip designs.