CAREER: Architectural Support for CPU / GPU Hybridization

职业：CPU / GPU 混合的架构支持

• 批准号: 1149539
• 负责人: Joseph Zambreno
• 金额: $ 46.63万
• 依托单位: Iowa State University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-04-01 至 2019-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1149539&HistoricalAwards=false
• 关键词: CAREER; Architectural; Support; CPU; GPU

One of the fundamental challenges facing the processor industry today is in continuing to address performance and scalability demands given the constraints of both energy and programmer efficiency. This CAREER project builds upon recently-introduced fused designs, which incorporate conventional microprocessors and graphics processors in the same package, in order to address these challenges through the development of more programmable, flexible, scalable, and secure hybrid architectures. Towards this long-term goal, this project investigates techniques that minimize limitations of the traditional coprocessing model, including performance bottlenecks, vulnerable shared memory spaces, and inflexible resource management. Specifically, this project explores thread divergence caused by complex control-flow and memory access, thread migration between cores, hardware accelerator design for tasks beyond traditional graphics processing, and adding security safeguards to match what is currently available on conventional microprocessors. In addition, this project also examines a variety of instruction set extensions, accelerator architectures, and models of computation that have the potential to lead to significant efficiency and programmer flexibility improvements. The expected impact is that this CAREER project will one day bear fruit in the form of another new segment of the computing industry, one that specializes in hybrid architectures that can scale to thousands of independent threads, while maintaining the capabilities of a traditional multi-user operating system and middleware. Broadly speaking, by advancing the state-of-the-art in computer architecture, this research will lead to improvements in consumer devices in terms of size and form factor, energy efficiency and battery life, and complexity and graphical fidelity of supported applications. Similarly, the usage of these architectures to enable continued performance scaling has the potential to have wide-ranging societal impact, through the advancement of those fields (e.g. bioinformatics, climate modeling, business intelligence) that utilize high-performance computing to enable innovative discovery. This project also includes a focus on expanding an existing course that the PI has developed, that takes a novel approach in introducing graphics processing and architecture from a hardware design perspective.

当今处理器行业面临的根本挑战之一是，鉴于能源和程序员效率的限制，继续解决性能和可伸缩性需求。该职业项目建立在最近引入的融合设计的基础上，该设计将传统的微处理器和图形处理器纳入同一软件包，以通过开发更加可编程，灵活，可扩展和安全的混合体系结构来应对这些挑战。为了实现这一长期目标，该项目调查了最大程度地减少传统参与模型的局限性的技术，包括绩效瓶颈，脆弱的共享记忆空间和不灵活的资源管理。具体来说，该项目探讨了由复杂的控制流和内存访问，内核之间的线程迁移，用于传统图形处理以外的任务的硬件加速器设计以及添加安全保障措施以匹配常规微处理器当前可用的任务。此外，该项目还研究了各种指令集扩展，加速器体系结构和计算模型，它们有可能提高效率显着和程序员的灵活性提高。预期的影响是，这个职业项目将有一天以计算行业的另一个新领域的形式承担成果，该项目专门从事混合体系结构，可以扩展到数千个独立线程，同时维护传统的多用户操作系统和中间件的功能。从广义上讲，通过推进计算机体系结构的最先进，这项研究将在大小和外形，能源效率和电池寿命以及支持应用程序的复杂性和图形忠诚度方面改善消费设备。同样，通过这些领域的发展（例如，生物信息学，气候建模，商业智能）来利用高性能计算来启用创新发现，对这些体系结构的持续绩效扩展可以产生广泛的社会影响。该项目还关注扩展PI开发的现有课程，该课程从硬件设计的角度引入图形处理和体系结构采用了一种新颖的方法。

项目成果

Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection

• DOI: 10.1145/3225058.3225104
• 发表时间: 2018-08
• 期刊: Proceedings of the 47th International Conference on Parallel Processing
• 作者: Xian Zhu;R. Wernsman;Joseph Zambreno

An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators

• DOI: 10.1109/asap.2019.000-2
• 发表时间: 2019-07
• 期刊: 2019 IEEE 30th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
• 作者: Saunak Saha;Henry Duwe;Joseph Zambreno