Design and Implementation of Algorithms for an Experimental High-Radix Network Switching system

计算机硬件的技术和经济趋势导致了今天广泛采用超大型多核服务器集群。的超级计算机。当应用程序被修改以利用这些额外节点和核心的并行性增加时，应用程序？的网络消息通常变得更小且更频繁。 尽管当前超级计算机系统中互连网络的带宽几乎跟上计算性能的增长，但发送消息的开销几乎没有改善，并且相应地，当发送短消息时，网络的吞吐量也几乎没有改善。 由于这两种趋势，许多应用在现有的超级计算系统上的扩展性很差，并且随着行业向更大的超级计算机系统发展，预计更多的应用将扩展性很差。在这项研究中，TACC正在研究一种新的网络交换机和网络接口架构，可以使用非常短的消息来维持全网络带宽，从而解决这些问题。 该项目正在研究有效使用该网络所需的编程模型，并通过与目前超级计算机中广泛使用的现代（四倍数据速率Infiniband）互连直接比较来评估新互连网络的性能，通过一些案例研究对新系统进行评估。由于网络性能限制，已知在标准系统上表现出较差的并行扩展性的算法的实现被移植到新系统中，并配备定时器和硬件性能计数器以记录详细的性能特征。这项研究将提供一个初步的技术可行性评估，目前实施的这种新的架构，这些算法，并预计将提供建议，为未来的增强架构。

Technology and economic trends in computer hardware have led to the widespread adoption of extremely large clusters of multicore servers as today?s supercomputers. As applications are modified to exploit the increased parallelism of these additional nodes and cores, the application?s network messages typically become both smaller and more frequent. Although the bandwidth of the interconnect networks in current supercomputer systems is almost keeping up with increases in compute performance, there has been little improvement in the overhead of sending messages, and correspondingly little improvement in the throughput of the network when sending short messages. As a consequence of these two trends, many applications scale poorly on existing supercomputing systems, and many more applications are expected to scale poorly as the industry moves forward with even larger supercomputer systems. In this study, TACC is investigating a possible solution to these issues with a new network switch and network interface architecture that can sustain full network bandwidth using very short messages. This project is investigating the programming models required to use this network efficiently and is evaluating the performance of the new interconnect network in direct comparison with a modern (quad-data-rate Infiniband) interconnect that is widely used in current supercomputers.The evaluation of the new system is being conducted through a number of case studies. Implementations of algorithms known to exhibit poor parallel scaling on standard systems due to network performance limitations are being ported to the new system and instrumented with timers and hardware performance counters to document the detailed performance characteristics. This study will provide an initial evaluation of the technical viability of the current implementation of this new architecture for these algorithms, and is expected to provide recommendations for future enhancements to the architecture.