SBIR Phase I: EI/ES6: Low Power Consumption Digital IC Systems

SBIR 第一阶段：EI/ES6：低功耗数字 IC 系统

• 批准号: 1249016
• 负责人: Richard Rubinstein
• 金额: $ 15万
• 依托单位: Granite Mountain Technologies
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-01-01 至 2013-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1249016&HistoricalAwards=false
• 关键词: SBIR; Phase; EI; ES6; Low

This Small Business Innovation Program (SBIR) Phase I project commercializes a technology that reduces the energy consumption in digital electronics on average by a factor of three. The solution applies across the complete semiconductor marketplace. The power advantages are derived based on designing multi-synchronous digital electronics. A next generation design flow is developed for multi-synchronous systems based on a novel method called relative timing. Relative timing enables the application of the standard single clock frequency Electronic Design Automation (EDA) tools and flows to be seamlessly applied to the design of multiple timing domains in a single digital integrated circuit. No modifications to the standard cell libraries are required. Some additional EDA is necessary to support the extended concurrency and synchronization provided by additional multi-synchronous circuit Intellectual Property (IP) primitives. These IP blocks enable lower power, reduced area, and higher performance than single frequency designs. Timing constraints in these multi-synchronous systems are based on formal verification and therefore are proven correct and complete. System design productivity is enhanced due to design modularity. This project validates the method by developing a product-ready semiconductor design that demonstrates a significant competitive advantage in power, area, and performance against a traditional single frequency design. The broader impact/commercial potential of this project addresses the need for reduced energy consumption in digital electronics and is rooted in the exponential growth in transistors on integrated circuits. Previously, as designs became power limited, new transistor technologies were introduced. Each logic family provided lower power and better performance. No new transistor technology is on the horizon, making design contributions to energy efficiency critical. The localized efficiency of multi-synchronous design is one of very few design methods that provide significant energy reduction. Successful commercialization will result in this technology being applied across the semiconductor industry to products ranging from performance cloud compute servers to medical electronics and sensors. Industry wide growth will occur through EDA and custom circuit IP products that enable the development of multi-synchronous architectures. Open market and strategic partnerships with world class semiconductor companies for training, consulting, and early product development will reduce early risk and develop market acceptance. Ultra-low power medical applications such as digital hearing aid devices particularly benefit from multi-synchronous technology. Increased battery life reduces product cost and improves the quality of life for seniors and the disabled. Similarly, ultra-low power biomedical wireless sensors likewise provide societal benefit.

这项小型企业创新计划（SBIR）第一阶段项目将一项技术商业化，该技术将数字电子产品的能耗平均降低了三倍。该解决方案适用于整个半导体市场。在设计多同步数字电子器件的基础上，推导出功率优势。提出了一种基于相对定时方法的多同步系统新一代设计流程。相对定时使标准单时钟频率电子设计自动化（EDA）工具和流程的应用能够无缝地应用于单个数字集成电路中的多个定时域的设计。不需要修改标准单元库。需要一些额外的EDA来支持额外的多同步电路知识产权（IP）原语提供的扩展并发性和同步。与单频设计相比，这些IP块具有更低的功耗、更小的面积和更高的性能。这些多同步系统中的时间约束是基于形式验证的，因此被证明是正确和完整的。由于设计的模块化，提高了系统设计的效率。该项目通过开发一种产品就绪的半导体设计来验证该方法，该设计在功率、面积和性能方面与传统的单频设计相比具有显着的竞争优势。该项目的广泛影响/商业潜力解决了数字电子产品中降低能耗的需求，并植根于集成电路中晶体管的指数级增长。以前，由于设计受到功率限制，新的晶体管技术被引入。每个逻辑系列都提供了更低的功耗和更好的性能。没有新的晶体管技术在地平线上，使得设计对能源效率的贡献至关重要。多同步设计的局部效率是为数不多的能显著降低能耗的设计方法之一。成功的商业化将使这项技术应用于整个半导体行业的产品，从性能云计算服务器到医疗电子产品和传感器。整个行业的增长将通过EDA和定制电路IP产品实现，这些产品能够开发多同步架构。开放市场，与世界级半导体公司建立战略合作伙伴关系，进行培训、咨询和早期产品开发，将降低早期风险，提高市场接受度。数字助听器等超低功耗医疗应用尤其受益于多同步技术。电池寿命的延长降低了产品成本，提高了老年人和残疾人的生活质量。同样，超低功耗生物医学无线传感器也提供了社会效益。