Lifetime Reliability of Systems-on-Chip: Unified Modeling and Dynamic Reliability Management

片上系统的寿命可靠性：统一建模和动态可靠性管理

• 批准号: 1263438
• 负责人: Cristinel Ababei
• 金额: $ 17.33万
• 依托单位: SUNY at Buffalo
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-08-16 至 2013-11-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1263438&HistoricalAwards=false
• 关键词: Lifetime; Reliability; Systems; Chip; Unified

Future integrated circuits will contain tens, hundreds, or even thousand cores per chip. However, technology downscaling that can make this possible may also make the underlying hardware less reliable due to an increasing number of defects and wear out mechanisms. Therefore, one of the major problems facing the design of multiprocessor systems-on-chip is reliability. Because either the cores or the network-on-chip (used for communication between the cores) can become a reliability bottleneck for these systems, it is imperative that the reliability be addressed in a unified manner. To address the reliability challenge, this research develops a novel unified theoretical lifetime reliability modeling framework. This framework is based on efficient Monte Carlo methods to treat multiprocessor systems-on-chip as a combination of computation and communication units. The goal of this research is to develop new dynamic reliability management techniques based on dynamic voltage and frequency scaling and application remapping. Based on control theory concepts, these techniques proactively improve the lifetime reliability of multicore systems.The proposed dynamic reliability management techniques enable the development of more reliable multiprocessor systems-on-chip, which have a dramatic impact on society via applications ranging from entertainment and gaming to bio-engineering, military and space. More broadly, the results of this project impact significantly the design of future integrated systems by advancing the understanding of the tradeoffs between reliability as a new design concern and power consumption, performance and area as traditional objectives.

未来的集成电路每个芯片将包含数十个、数百个甚至数千个核心。然而，可以使这成为可能的技术缩小也可能使底层硬件由于越来越多的缺陷和磨损机制而变得不那么可靠。因此，多处理器片上系统设计面临的主要问题之一是可靠性。由于内核或片上网络（用于内核之间的通信）可能成为这些系统的可靠性瓶颈，因此必须以统一的方式解决可靠性问题。为了解决可靠性的挑战，本研究开发了一种新的统一的理论寿命可靠性建模框架。这个框架是基于有效的蒙特卡罗方法来处理多处理器系统芯片的计算和通信单元的组合。本研究的目的是发展新的动态可靠性管理技术的基础上动态电压和频率缩放和应用重映射。基于控制理论的动态可靠性管理技术可以提高多核系统的寿命可靠性，使多处理器片上系统的可靠性得到进一步提高，并在娱乐、游戏、生物工程、军事和航天等领域产生巨大的社会影响。更广泛地说，这个项目的结果影响显着未来的集成系统的设计，通过推进作为一个新的设计关注和功耗，性能和面积作为传统的目标之间的权衡的理解。