CAREER: Integrated Research and Education in Physical Design Automation for Nanotechnology and VLSI Technology Co-Design

这份职业建议书旨在开发关于纳米技术互连和铜互连共同设计的创新芯片布局设计和优化方法。随着铜互连技术接近其基本物理极限，碳纳米管和石墨烯纳米带等新型片上互连材料因其优异的导电性和抗电迁移能力等性能而成为有希望的替代材料，否则这些性能一直困扰着铜互连。另一方面，使用纳米技术互连也可能存在一些问题，例如它们作为局部互连的性能较差，以及制造中的缺陷。PI将开发一种新颖的协同设计方法，将纳米技术巧妙地整合到实际的VLSI电路设计中，并在协同设计感知缓冲、层分配、布线、布局和时钟方面采用各种使能技术。PI还提出了缺陷感知技术来减轻缺陷对纳米互连的影响，并提高了对故障的鲁棒性。所提出的研究的更广泛的影响是显著提高纳米级电路的电路性能。由于互连时延是影响电路时延的主要因素，因此对于那些时序无法关闭的困难电路，即使各种传统的物理综合优化已经被最大限度地拉长，所提出的研究也有可能实现设计闭包。建议的研究可为集成电路设计方法作出贡献，使纳米技术能够应用于实际电路设计，以打破目前流行的VLSI技术的基本限制。该中心亦会发展研究与教育的无缝结合，例如发展新的研究生课程、发展系列讲座和研讨会、招收人数不足的学生，以及在会议上展示研究成果。

This CAREER proposal aims to develop innovative chip layout design and optimization methodologies on nanotechnology interconnect and copper interconnect co-design. As the copper interconnect technology is approaching its fundamental physical limit, novel on-chip interconnect materials such as carbon nanotubes and graphene nano-ribbons have emerged as promising replacement materials due to properties such as superior conductivity and resilience to electromigration that otherwise have plagued copper interconnects. On the other hand, there could also be some issues for using nanotechnology interconnects such as their inferior performance as local interconnect and defects in fabrication. The PI will develop a novel co-design methodology which judiciously integrates nanotechnology into the practical VLSI circuit design together with various enabling techniques on co-design-aware buffering, layer assignment, routing, placement and clocking. The PI also proposes defect-aware techniques for mitigating the impacts due to defects, and improving robustness against faults for nanotechnology interconnects.The broader impact of the proposed research is to significantly improve the circuit performance of nanoscale circuits. As the interconnect delay is the dominating factor of the circuit delay, the proposed research has the potential to help achieve the design closure for those difficult circuits whose timing cannot be closed even if various traditional physical synthesis optimizations have been stretched to the maximum extent. The proposed research can contribute integrated circuit design methodologies which enable the utilization of nanotechnologies into practical circuit design to defeat the fundamental limit on the prevailing VLSI technology. The PI will also develop a seamless integration of research with education such as developing the new graduate level course, developing lecture series and seminars, recruiting under-represented students, and showcasing the research results at conferences.