Large-Scale Fabrication of Multi-Nanopillar Transistors for Energy-Efficient Electronics

一项能够大幅减少电子设备运行中的能源消耗的技术将有望实现许多商业、军事和空间应用。例如，智能手机、笔记本电脑和平板电脑的能耗减少10倍，电池充电频率就会减少10倍。然而，由于当前电子设备通常使用的晶体管体系结构的限制，获得这样的设备能耗的降低一直是具有挑战性的。该奖项将研究一种新的晶体管技术，在这种技术中，晶体管组件在一个纳米级的柱子内制造，其工作原理允许电子以非常低的能耗流动。该项目的成功实施将大大减少家庭、办公室、商店、机场等电子系统的能源消耗，总体上将使美国的经济、环境和社会受益。预计还将带来各种军事好处，如士兵在执行任务时携带的更轻、更节能的电子设备，提高他们的作战能力，加强我们国家在国内外的安全。在现代电子设备的大规模集成电路中，大量的能量消耗或散热是阻碍电子设备技术进步的关键问题。其根本原因是电子的热激发，这对启用陡峭的开关施加了限制，导致了大量的能源消耗。该项目研究了一种新型晶体管，它有效地抑制了电子的热激发，使得在室温下可以获得陡峭的通断开关能力，从而大大降低了晶体管运行中的能耗。晶体管将被构建为单纳米管，每个纳米管包含所有晶体管组件，如源极、量子阱、隧道势垒、半导体岛和漏极。量子阱中的分立态将作为能量过滤器，阻止高能电子的传输，并有效地抑制电子的热激发。重要的是，纳米晶体管将被大规模制造，结合了与CMOS兼容的并行工艺和自下而上的纳米组装，该组装利用自限静电纳米颗粒放置技术，其中纳米颗粒被用作腐蚀硬掩模，以生产可单独寻址的纳米晶。

A technology that enables substantial reduction of energy consumption in the operation of electronic devices would promise numerous commercial, military and space applications. For example, ten-fold reduction of energy consumption for smart phones, laptops and tablets could result in ten-fold reduction in frequency of battery recharging. However, obtaining such reductions in device energy consumption has been challenging due to limitations of the transistor architecture that current electronic devices commonly use. This award will investigate a new transistor technology in which the transistor components are made within a single nanoscale pillar and whose operating principle allows electrons to flow with very little energy consumption. A successful execution of this project will enable significant reductions in energy consumption by electronic systems at home, office, store, airport, etc., which will benefit the U.S. economy, environment and society, in general. Various military benefits are also expected, such as, lightweight, more energy-efficient electronic equipment that soldiers carry in their missions, increasing their combat capabilities, enhancing the security of our nation at home and abroad. A large amount of energy consumption or heat dissipation in the large-scale integrated circuits of modern electronic devices is a critical problem that inhibits the advancement of electronic device technology. Its root cause is the thermal excitation of electrons, which imposes limitations on enabling steep ON/OFF switching, resulting in a large amount of energy consumption. This project investigates a new transistor in which the electron thermal excitation is effectively suppressed so that steep ON/OFF switching capability can be obtained at room temperature, leading to substantial reduction of energy consumption in the transistor operation. The transistors will be constructed as single nanopillars, with each nanopillar containing all the transistor components, such as source, quantum well, tunneling barrier, semiconductor island and drain. A discrete state in the quantum well will serve as an energy filter, which blocks the transport of energetic electrons and effectively suppresses the electron thermal excitation. Importantly, the nanopillar transistors will be fabricated on a large scale combining CMOS-compatible parallel processes and bottom-up assembly of nanoparticles that utilizes self-limiting electrostatic nanoparticle placement technique, where the nanoparticles are used as etch hard masks for producing individually addressable nanopillars.