Large-Scale Fabrication of Multi-Nanopillar Transistors for Energy-Efficient Electronics

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A technology that enables substantial reduction of energy consumption in the operation of electronic devices would promise numerous commercial, military and space applications. For example, ten-fold reduction of energy consumption for smart phones, laptops and tablets could result in ten-fold reduction in frequency of battery recharging. However, obtaining such reductions in device energy consumption has been challenging due to limitations of the transistor architecture that current electronic devices commonly use. This award will investigate a new transistor technology in which the transistor components are made within a single nanoscale pillar and whose operating principle allows electrons to flow with very little energy consumption. A successful execution of this project will enable significant reductions in energy consumption by electronic systems at home, office, store, airport, etc., which will benefit the U.S. economy, environment and society, in general. Various military benefits are also expected, such as, lightweight, more energy-efficient electronic equipment that soldiers carry in their missions, increasing their combat capabilities, enhancing the security of our nation at home and abroad. A large amount of energy consumption or heat dissipation in the large-scale integrated circuits of modern electronic devices is a critical problem that inhibits the advancement of electronic device technology. Its root cause is the thermal excitation of electrons, which imposes limitations on enabling steep ON/OFF switching, resulting in a large amount of energy consumption. This project investigates a new transistor in which the electron thermal excitation is effectively suppressed so that steep ON/OFF switching capability can be obtained at room temperature, leading to substantial reduction of energy consumption in the transistor operation. The transistors will be constructed as single nanopillars, with each nanopillar containing all the transistor components, such as source, quantum well, tunneling barrier, semiconductor island and drain. A discrete state in the quantum well will serve as an energy filter, which blocks the transport of energetic electrons and effectively suppresses the electron thermal excitation. Importantly, the nanopillar transistors will be fabricated on a large scale combining CMOS-compatible parallel processes and bottom-up assembly of nanoparticles that utilizes self-limiting electrostatic nanoparticle placement technique, where the nanoparticles are used as etch hard masks for producing individually addressable nanopillars.