SHF: Conference: Hardware and Algorithms for Learning On-a-chip; November 5, 2015; Austin, TX

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Support for student participation in a workshop to establish a forum for discussion of the current practices, as well as future research needs in three interrelated subareas of brain related sciences is provided through this grant. The three specific subareas that the workshop will discuss are: hardware acceleration of on-chip learning; machine learning algorithms and neuro-inspired information processing; and nano-electronic design for learning, with the focus on performance and energy efficiency. The workshop will consist of three sessions and will be followed by a panel discussion, and will end with a poster session to present student work. The conference will not only provide a venue for researchers to address problems but also a platform for graduate students and others to learn about cutting-edge research by attending invited talks, presentations, tutorials in the general area.The outcome of this workshop include a webpage hosted by the Arizona State University to disseminate the program and discussions, as well as a report that clearly identifies major research challenges and needs in computational neurosciences, machine learning, and hardware design. The papers and posters will be published through the workshop proceedings. These results will illustrate new and exciting inter-disciplinary research problems of interest to the related communities, and articulate a vision of conducting further research in this area. The final workshop report will also be submitted to NSF as an annual report and will be released online for sharing with the research community in general.