Heterogeneous III-V CMOS on Si via Direct Growth

通过直接生长在 Si 上实现异质 III-V CMOS

• 批准号: 1610604
• 负责人: Rehan Kapadia
• 金额: $ 30万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2016
• 资助国家: 美国
• 起止时间: 2016-08-01 至 2021-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1610604&HistoricalAwards=false
• 关键词: Heterogeneous; III; CMOS; Si; via

III-V semiconductors hold performance records for a vast majority of electronic and photonic device categories, from transistor speed to photovoltaic conversion efficiency. However, the inability to cost-effectively integrate high material quality III-V's with substrates amenable to volume manufacturing, such as Si wafers has limited the adoption of III-V materials to applications that can absorb the high costs of III-V growth. This limitation arises from the fundamental lattice mismatch between the III-V semiconductors of interest and the underlying Si substrate. While a variety of approaches have been developed to address this challenge, they often rely on complex buffer layers and face challenges when tightly integrating different materials on the same layer. Here, a recently developed growth technique that enables growth of crystalline III-V's on non-lattice matched substrates will be utilized to demonstrate heterogeneous III-V CMOS logic circuits on Si. Importantly, the technique used here will potentially dramatically reduce the cost of III-V integration. In addition to the specific demonstration of logic circuits, the integration of III-Vs with Si can potentially impact a wide ranges of areas such as photonics, sensing, and photovoltaics. To advance STEM education and diversity as part of this project, a joint effort with a local high school is being undertaken to build integrated physics and math lesson plans that aid students in seeing how complex math concepts are utilized to build models for the physical world. The specific goal of this research is to demonstrate indium phosphide, indium arsenide, and gallium antimonide based III-V CMOS logic circuits directly grown on Si substrates. Critically, the growth studied here involves precipitation of the desired III-V crystal out of a liquid phase metal solvent, in contrast to the vapor-solid growth phases used for traditional MOCVD growth. This work will be carried out by first performing detailed structural and electronic material characterization of III-Vs grown on Si, using techniques such as x-ray diffraction, transmission electron microscopy, electron backscatter diffraction, Hall measurements, photoluminescence yield, and time resolved photoluminescence measurements. Utilizing these techniques, we will establish how growth parameters affect the formation of defects in the III-Vs, and how those defects impact the optoelectronic characteristics of the materials. Finally, III-V n-channel and p-channel FinFETs and circuits will be fabricated and characterized focusing on both individual devices and materials co-integration issues. Furthermore, the materials and processes developed here will be of importance for a wide range of fields including electronics, photonics, imaging, and photovoltaics.

III-V半导体在绝大多数电子和光子器件类别中保持着性能记录，从晶体管速度到光伏转换效率。然而，无法成本有效地将高材料质量III-V族与适合批量制造的衬底（例如Si晶片）集成，这限制了III-V族材料在能够吸收III-V族生长的高成本的应用中的采用。这种限制是由感兴趣的III-V族半导体和下面的Si衬底之间的基本晶格失配引起的。虽然已经开发了各种方法来解决这一挑战，但它们通常依赖于复杂的缓冲层，并且在同一层上紧密集成不同材料时面临挑战。在这里，最近开发的生长技术，使非晶格匹配的衬底上的晶体III-V的生长将被用来证明异质III-V CMOS逻辑电路在Si上。重要的是，这里使用的技术可能会大大降低III-V集成的成本。除了逻辑电路的具体演示外，III-V与Si的集成可能会影响广泛的领域，如光子学，传感和光电学。作为该项目的一部分，为了推进STEM教育和多样性，正在与当地一所高中共同努力，建立综合的物理和数学课程计划，帮助学生了解如何利用复杂的数学概念为物理世界建立模型。这项研究的具体目标是展示磷化铟，砷化铟，锑化镓的III-V CMOS逻辑电路直接生长在硅衬底上。重要的是，这里研究的生长涉及从液相金属溶剂中沉淀出所需的III-V族晶体，与用于传统MOCVD生长的气-固生长相相反。这项工作将首先进行详细的结构和电子材料表征的III-V生长在Si上，使用技术，如X射线衍射，透射电子显微镜，电子背散射衍射，霍尔测量，光致发光产率，和时间分辨光致发光测量。利用这些技术，我们将确定生长参数如何影响III-V中缺陷的形成，以及这些缺陷如何影响材料的光电特性。最后，III-V族n沟道和p沟道FinFET和电路将被制造和表征，重点关注单个器件和材料的协集成问题。此外，这里开发的材料和工艺将对包括电子学、光子学、成像和光电子学在内的广泛领域具有重要意义。