SaTC: CORE: Small: Collaborative: Hardware Architectures for Post-Quantum Cryptography

本研究计画针对后量子安全密码演算法（PQC）提出新的硬体设计与实作。虽然今天用于公钥密码学的算法，例如RSA算法或数字签名很容易被量子计算机的“密码分析”破解，但PQC算法提供了对这种密码分析的保护，因为它们不能在量子计算机上被破解。为了了解如何从能量、面积和性能的角度创建最高效的硬件PQC设计，该项目将新算法实现为定制的专用集成电路。这项工作的重点是硬件设计方面的PQC算法，在很大程度上是未开发的。该项目通过开展专业和教育活动，特别促进硬件安全和集成电路研究人员之间以及更广泛的受众之间的思想发展和交流。 为了提高对PQC算法的理解，本项目开发了基于代码的算法的FPGA实现以进行评估。 新的设计模块，如高斯消除，或多项式评估与加法FFT的开发，以创建新的和有效的硬件原语。通过VLSI设计流程的设计，以实现集成电路的功率，面积和性能进行评估。 大型存储器的问题，所需的PQC算法使用的大密钥，以及与其他计算平台的集成电路的合并，以创建硬件加速器的PQC算法。该项目可能有助于正在进行的美国和国际算法标准化工作。

This research project develops new hardware designs and implementations for a class of post-quantum secure cryptographic (PQC) algorithms. While today's algorithms used for public key cryptography, e.g. the RSA algorithm, or digital signatures are vulnerable to being broken through "cryptanalysis" using quantum computers, PQC algorithms offer protections from such cryptanalysis as they cannot be broken on a quantum computer. To understand how to create the most efficient hardware PQC designs from energy, area, and performance perspective, this project realizes the new algorithms as custom application specific integrated circuits. This work focuses on hardware design aspect of PQC algorithms that has been largely unexplored. This project especially promotes development and exchange of ideas between hardware security and integrated circuit researchers and among a broader audience through development of professional and educational activities. To advance the understanding of the PQC algorithms, this project develops FPGA implementations of the code-based algorithms for evaluation. Novel designs for modules such as Gaussian Elimination, or polynomial evaluation with Additive FFT are developed, to create new and efficient hardware primitives. The designs are taken through VLSI design flow to realize the integrated circuits that are evaluated for power, area, and performance. Issues of large memories, needed for the large keys used by the PQC algorithms, are addressed as well as incorporation of the integrated circuits with other computing platforms to create hardware accelerators for the PQC algorithms. This project may contribute to the ongoing US and international algorithm standardization efforts.