SHF:SMALL: MECAR: Memory-Centric Architecture to Bridge the Gap Between Computing and Memory

SHF:SMALL：MECAR：以内存为中心的架构，弥合计算和内存之间的差距

• 批准号: 1719160
• 负责人: Yufei Ding
• 金额: $ 45万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-07-15 至 2021-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1719160&HistoricalAwards=false
• 关键词: SHF; SMALL; MECAR; Memory; Centric

Traditional computer systems usually follow the so-called classic Von Neumann architecture, with separated processing units (such as CPUs and GPUs) to do computing and memory units for data storage.  The increasing gap between the computing of processor and the memory has created the memory wall problem in which the memory subsystem is becoming the bottleneck of the entire computing system. As technology scales, data movement between the processing units (PUs) and the memory is becoming one of the most critical performance and energy bottlenecks in various computer systems, ranging from cloud servers to end-user devices. As we enter the era of big data, many emerging data-intensive workloads become pervasive and mandate very high bandwidth and heavy data movement between the computing units and the memory.  The fundamental goal of this project is to advance the trend of bridging the gap between computing and memory, with an application-driven approach. By leveraging the PI's prior extensive research on 3D-stacked memory and non-volatile memory architecture, the PI proposes to focus on (1) designing memory-centric processing unit (PU) architecture with massive GB on-chip/on-package memory integrated with computing units; (2) investigating new processing-in-memory(PIM) memory architecture designs with both DRAM and emerging NVM; (3) and co-design and co-optimization of both memory-centric PU architecture and NDC/PIM memory architecture, with the emerging data-intensive applications such as neural computing and graph analytics as application driver to guide the architecture optimization. The success of this research will have enormous economic and social benefits as broader impact. The research will provide the design guidelines for enabling future computing systems beyond the state-of-the-art, ranging from high performance exascale computing to low power mobile systems. Consequently, it will enhance nearly every digital device available today from consumer to enterprise electronics. It can also spawn new applications involving the computation on the exascale of data, e.g. data mining, machine learning, bio-informatics, etc. It is expected that this project will serve as a catalyst to accelerate the adoption of data-intensive and memory-centric technologies in future computer systems and applications from architecture and system design perspectives. The PI has extensive industrial ties with summer internships planned, which will be invaluable for broadening the knowledge and skills of the students. The PI will also strive to educate a broad audience on the emerging technologies through regular and online classes. Publication/lecture notes will be released on public websites to promote the broader dissemination of scientific knowledge.

传统计算机系统通常遵循所谓的经典冯·诺伊曼架构，具有独立的处理单元（如CPU和GPU）来做计算和存储数据的内存单元。处理器和内存之间的计算差距越来越大，造成了内存墙问题，其中内存子系统正在成为整个计算系统的瓶颈。随着技术规模的扩大，处理单元（PU）和存储器之间的数据移动正在成为从云服务器到终端用户设备的各种计算机系统中最关键的性能和能量瓶颈之一。随着我们进入大数据时代，许多新兴数据-密集型工作负载变得无处不在，并要求非常高的带宽和计算单元与内存之间的大量数据移动。该项目的基本目标是以应用程序驱动的方法，推动弥合计算与存储器之间差距的趋势。通过利用PI先前对3D堆栈存储器和非易失性存储器架构的广泛研究，PI建议专注于（1）设计以存储器为中心的处理单元（PU）架构，其具有与计算单元集成的大容量GB片上/封装上存储器;（2）研究具有DRAM和新兴NVM两者的新的存储器内处理（PIM）存储器架构设计;（3）以内存为中心的PU架构和NDC/PIM内存架构的协同设计和协同优化，与新兴数据-神经计算和图形分析等密集型应用作为应用驱动程序，以指导架构优化。这项研究的成功将具有巨大的经济效益和社会效益，影响广泛。这项研究将提供设计指南，使未来的计算系统超越国家的最先进的，从高性能的艾级计算到低功耗的移动的系统。因此，它将增强当今几乎所有的数字设备，从消费电子到企业电子。预期该项目将成为催化剂，从架构和系统设计的角度，加速在未来计算机系统和应用中采用数据密集和以内存为中心的技术。PI与计划中的暑期实习有广泛的行业联系，这对扩阔学生的知识和技能是非常宝贵的。PI也将致力通过定期和在线课程向广大受众介绍新兴技术。将在公共网站上发布出版物/讲义，以促进更广泛地传播科学知识。

项目成果

MEDAL: Scalable DIMM based Near Data Processing Accelerator for DNA Seeding Algorithm

• DOI: 10.1145/3352460.3358329
• 发表时间: 2019-10
• 期刊: Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture
• 作者: Wenqin Huangfu;Xueqi Li;Shuangchen Li;Xing Hu;P. Gu;Yuan Xie

iPIM: Programmable In-Memory Image Processing Accelerator Using Near-Bank Architecture

• DOI: 10.1109/isca45697.2020.00071
• 发表时间: 2020-05
• 期刊: 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
• 作者: P. Gu;Xinfeng Xie;Yufei Ding;Guoyang Chen;Weifeng Zhang;Dimin Niu;Yuan Xie

Timely: Pushing Data Movements And Interfaces In Pim Accelerators Towards Local And In Time Domain

• DOI: 10.1109/isca45697.2020.00073
• 发表时间: 2020-05
• 期刊: 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
• 作者: Weitao Li;Pengfei Xu;Yang Zhao;Haitong Li;Yuan Xie;Yingyan Lin

DUET: Boosting Deep Neural Network Efficiency on Dual-Module Architecture

• DOI: 10.1109/micro50266.2020.00066
• 发表时间: 2020-10
• 期刊: 2020 53rd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
• 作者: Liu Liu-Liu;Zheng Qu;Lei Deng;Fengbin Tu;Shuangchen Li;Xing Hu;Zhenyu Gu;Yufei Ding;Yuan Xie

Boosting Deep Neural Network Efficiency with Dual-Module Inference

• 发表时间: 2020-07
• 作者: Liu Liu-Liu;Lei Deng;Zhaodong Chen;Yuke Wang;Shuangchen Li;Jingwei Zhang;Yihua Yang;Zhenyu Gu;Yufei Ding;Yuan Xie