SHF:SMALL: MECAR: Memory-Centric Architecture to Bridge the Gap Between Computing and Memory

传统的计算机系统通常遵循所谓的经典冯·诺伊曼架构，使用独立的处理单元（如cpu和gpu）进行计算，并使用存储数据的存储单元。随着处理器计算能力与存储器计算能力之间的差距越来越大，产生了存储器墙问题，存储器子系统正在成为整个计算系统的瓶颈。随着技术的发展，处理单元（pu）和内存之间的数据移动正成为各种计算机系统（从云服务器到最终用户设备）中最关键的性能和能源瓶颈之一。随着我们进入大数据时代，许多新兴的数据密集型工作负载变得无处不在，并且需要在计算单元和内存之间进行非常高的带宽和大量数据移动。该项目的基本目标是通过应用程序驱动的方法，推动弥合计算和内存之间差距的趋势。通过利用PI先前对3d堆叠存储器和非易失性存储器架构的广泛研究，PI建议将重点放在(1)设计以存储器为中心的处理单元（PU）架构，将大量GB片上/包上存储器与计算单元集成；(2)研究新的内存处理（PIM）内存架构设计，包括DRAM和新兴的NVM；(3)以内存为中心的PU架构和NDC/PIM内存架构协同设计和协同优化，以神经计算和图形分析等新兴数据密集型应用为应用驱动，指导架构优化。这项研究的成功将产生巨大的经济和社会效益，并产生更广泛的影响。该研究将提供设计指南，使未来的计算系统超越最先进的技术，范围从高性能百亿亿次计算到低功耗移动系统。因此，它将增强几乎所有现有的数字设备，从消费者到企业电子产品。它还可以产生新的应用，涉及到百亿亿级数据的计算，例如数据挖掘、机器学习、生物信息学等。预计该项目将从架构和系统设计的角度加速未来计算机系统和应用中采用数据密集型和以内存为中心的技术。PI与暑期实习计划有着广泛的工业联系，这对拓宽学生的知识和技能将是无价的。PI还将努力通过定期和在线课程向广大受众普及新兴技术。出版物/讲稿将在公共网站上发布，以促进科学知识的广泛传播。

Traditional computer systems usually follow the so-called classic Von Neumann architecture, with separated processing units (such as CPUs and GPUs) to do computing and memory units for data storage.  The increasing gap between the computing of processor and the memory has created the memory wall problem in which the memory subsystem is becoming the bottleneck of the entire computing system. As technology scales, data movement between the processing units (PUs) and the memory is becoming one of the most critical performance and energy bottlenecks in various computer systems, ranging from cloud servers to end-user devices. As we enter the era of big data, many emerging data-intensive workloads become pervasive and mandate very high bandwidth and heavy data movement between the computing units and the memory.  The fundamental goal of this project is to advance the trend of bridging the gap between computing and memory, with an application-driven approach. By leveraging the PI's prior extensive research on 3D-stacked memory and non-volatile memory architecture, the PI proposes to focus on (1) designing memory-centric processing unit (PU) architecture with massive GB on-chip/on-package memory integrated with computing units; (2) investigating new processing-in-memory(PIM) memory architecture designs with both DRAM and emerging NVM; (3) and co-design and co-optimization of both memory-centric PU architecture and NDC/PIM memory architecture, with the emerging data-intensive applications such as neural computing and graph analytics as application driver to guide the architecture optimization. The success of this research will have enormous economic and social benefits as broader impact. The research will provide the design guidelines for enabling future computing systems beyond the state-of-the-art, ranging from high performance exascale computing to low power mobile systems. Consequently, it will enhance nearly every digital device available today from consumer to enterprise electronics. It can also spawn new applications involving the computation on the exascale of data, e.g. data mining, machine learning, bio-informatics, etc. It is expected that this project will serve as a catalyst to accelerate the adoption of data-intensive and memory-centric technologies in future computer systems and applications from architecture and system design perspectives. The PI has extensive industrial ties with summer internships planned, which will be invaluable for broadening the knowledge and skills of the students. The PI will also strive to educate a broad audience on the emerging technologies through regular and online classes. Publication/lecture notes will be released on public websites to promote the broader dissemination of scientific knowledge.