EAGER: Designing Novel Polymorphic Gates as Hardware Security Primitives

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Conventional digit logic gates will generate a deterministic output signal for a given set of input signals (called input vector). Polymorphic gates are different in the sense that their output for the same input vector may vary depending on the operating environment such as temperature, voltage, and humidity. So we can consider polymorphic gates as logic gates that can implement multiple functions and behave as one of them according to certain controllable factors. This happens because polymorphic gates have unconventional structure at the transistor level. However, such unconventional structure is hard to find as it has been demonstrated by researchers since this concept was proposed by NASA researchers in 2001 in an effort to minimize chip area of the design. In this EAGER project, we propose to investigate systematic methods to construct novel polymorphic gates for Internet of Things (IoT) and cybersecurity applications. This project will focus on the development of three enabling technologies to establish polymorphic gates as a hardware security primitive. First, since polymorphic gates are rare, how can researchers construct sufficient types of them so we can integrate them into the conventional CMOS technology as well as new nano-technology? We will answer this question by studying the novel concept of partial polymorphic gates and the associated evolutionary algorithms to find the transistor structure that implements such polymorphic gates. Second, what security applications can benefit from the polymorphic gates? We propose to demonstrate the great promise of polymorphic gates as a hardware security primitive on several concrete cybersecurity applications, such as intellectual property protection, circuit obfuscation, device authentication, and random number generation. Third, how good is polymorphic gates based security? We will conduct both theoretical and empirical analysis on the proposed security applications with proper attack models and potential countermeasures. Any success from this EAGER project will be revolutionary to the research community that is interested in polymorphic gates and their applications, hardware security, evolutionary algorithms, device physics and circuit theory.