CAREER: Revamping the Memory Systems for Efficient Data Movement

数据移动效率目前是科学计算下一次性能飞跃和大数据分析下一次质量改进的最具挑战性的障碍之一。数据移动的低效率根源于传统的存储器系统设计，其基于应用具有良好局部性的假设，并且由克服存储器延迟墙的主要目标指导。这种设计原则导致了从顶层到底层逐步增加访问粒度的存储器层次结构设计。在存储器层次结构的一个级别处的访问将连续的数据块移动到另一个级别以受益于空间局部性。然而，随着处理器核的数量增加，由于在存储器层次结构的所有级别处的竞争增加以及执行环境的动态性质，仅通过程序员的努力或编译器优化难以实现良好的存储器局部性。即使对于高度优化的代码，内存块的平均利用率也不到12%，这导致了能量、带宽和片上存储的浪费。为了提高数据移动效率，该项目旨在改造内存系统，以主动创建和重新定义硬件中的位置。 这项研究有可能通过新的内存系统设计从根本上提高数据移动效率，这也可以激发对编程语言、编译器和运行时系统设计的全面反思。本项目还将对研究生和本科生进行培训和指导，在女性和代表性不足的群体中推广STEM，并开展外联活动，提高未来程序员和计算机工程师对数据移动效率问题的认识。本工作的目标是重新构建内存系统，通过利用细粒度访问相关性来提高数据移动效率。挑战在于，跟踪细粒度的相关性可能需要大量的Meta数据和控制开销。这项工作采取了端到端的方法来共享Meta数据和控制信号之间的不同层次的内存层次结构。在这项研究中开发了一类新的内存和高速缓存体系结构，重新定义的地方在每个层次的内存，提高数据移动，高速缓存存储效率和性能，而不会引入显着的开销。这项研究还调查了新的内存组织，以提高数据移动效率，在新兴的内存系统，如非易失性存储器和近内存处理系统。这项工作使用周期精确的架构模拟器和一组重要的数据密集型工作负载进行评估。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

Data movement efficiency is currently one of the most challenging impediments to the next performance leap in scientific computing and to the next qualitative improvement in big data analytics. The inefficiency of data movement is rooted in the conventional memory system design, which is based on the assumption that applications have good locality and is guided by the primary goal to overcome the memory latency wall. This design principle leads to a memory hierarchy design that progressively increases access granularity from the top to the bottom level. An access at one level of the memory hierarchy moves a contiguous block of data to another level to benefit from spatial locality. As the number of processor cores increases, however, good memory locality is difficult to achieve by programmer efforts or compiler optimizations alone, due to increasing contentions at all levels of the memory hierarchy and the dynamic nature of execution environments. The average utilization of a memory block is less than twelve percent even for highly optimized code, which results in a waste of energy, bandwidth, and on-chip storage. To improve data movement efficiency, this project seeks to revamp the memory systems to proactively create and redefine locality in hardware. This research holds the potential to fundamentally improve data movement efficiency through new memory system designs, which can motivate a complete rethinking of programming language, compiler, and run-time system designs as well. This project also seeks to train and mentor graduate and undergraduate students, promoting STEM among women and underrepresented groups, and developing outreach activities that raise awareness of the data movement efficiency problem among future programmers and computer engineers.The goal of this work is to re-architect the memory systems to improve data movement efficiency by exploiting fine-grain access correlations. The challenge is that tracking fine-grain correlations could require high meta data and control overheads. This work takes an end-to-end approach to share the meta data and control signals among different levels of the memory hierarchy. A new class of memory- and cache-architectures are developed in this research to redefine locality at each level of the memory hierarchy, which improves data movement, cache storage efficiency, and performance without introducing significant overheads. This research also investigates new memory organizations to improve data movement efficiencies in emerging memory systems such as non-volatile memory and near-memory processing systems. This work is evaluated using cycle-accurate architectural simulators and a set of important data-intensive workloads. Data structure- and algorithm- oriented optimizations are explored to allow existing and emerging workloads to take full advantage of the new memory architectures.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.