FoMR: Secure, Light-Weight Speculative Engines for Coordinated and Cohesive Speculation in Future Memory Systems

点击翻译按钮获取中文摘要

The scaling of computer systems through the next decade poses a grand challenge due to the slowing down of the decades-long trend of packing more processors into a given area at the same cost. In this new era, the benefits of improved manufacturing processes will largely end. Thus, processor performance must be won through processor design advancement. The goal of this research is to develop secure techniques to improve processors performance by accurately speculating on future memory references and data values. At a high level the research leverages light-weight speculation engines, speculating on program path and data values without the overheads of a full core, predicting reference patterns and speculating on read/write sets to alleviate memory latency effects on instruction-level parallelism (ILP) extraction. This project addresses a critical need for new architectural techniques which securely improve both power efficiency and ILP. Furthermore, this project addresses the need for computer engineers at all levels with an understanding of efficient, secure processor design, as the computer industry struggles to attract talent with the skills to meet these challenges.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.