EAGER: Feasibility Study of Epitaxial Oxide Resistive Field Effect Transistor (EOR-FET)

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The need to accelerate computing speed while maintaining the same or similar level of power consumption is one of the oldest and most challenging problems in microelectronics. In this EAGER project, an exploratory idea of using epitaxial perovskite oxide heterostructure is investigated as a novel platform for high performance, energy-efficient computing. The approaches developed in this proposal are creative and original because although there have been many research and development efforts on the new logic devices, there is minimal work on how oxide thin films can lead the way to better computing. Thus, if successful, this research will lead researchers to rethink the role of oxides in computing devices and ultimately contribute to tackling today's most significant computing challenge. In this project, an innovative device solution is introduced by synergistically combining multiple disciplines in advanced materials. The primary educational goal of this project is to directly integrate the state-of-the-art research outcome into the curriculum of UTSA, which is a research-intensive, Hispanic-serving institution. An educational barrier that has existed as a great challenge in training underrepresented minority students with project-based research is expected to be overcome by developing the virtual laboratory environment. The specific research objective of this proposal is to determine the best ways of constructing the electrostrictive field-effect transistor (FET) device structure and understand the main factors that contribute to its superior device performance in terms of speed, power, and reliability. Based on preliminary data, the central hypothesis is that the epitaxial oxide heterostructure, prepared by the advanced oxide-MBE (molecular beam epitaxy) technique, will achieve maximum strain transfer from the top piezoelectric gate oxide layer to the bottom memristive channel layer, thereby leading to successful demonstration of the electrostrictive FET. To test feasibility of such a novel device structure, both the theoretical and experimental approaches will be adopted to investigate each oxide layer as key components of the high-speed, low-power logic device. This research will enhance a fundamental understanding of how a piezoelectric material can be best matched with a channel material for maximum electrostrictive FET device performance. The proposed work is of great intellectual significance because ultimately, it will provide a right insight on how this innovative technology will be positioned as the next-generation logic as benchmarked with other existing or emerging device candidates.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.