STTR Phase I: Low-Cost Packaging Solution for Space-Grade and High-Reliability Integrated Circuits

这个小企业技术转让研究（STTR）第一阶段项目的更广泛的影响/商业潜力旨在为空间应用提供成本效益，紧凑和性能更高的集成电路。空间电子技术落后于商业最先进技术十多年。 缺乏高性能、高性价比的封装解决方案进一步扩大了这一差距。传统上，空间应用使用大型、昂贵且低性能的陶瓷封装，这限制了抗辐射半导体在“新空间”应用中的采用，例如用于全球互联网的低地球轨道（LEO）巨型星座。为卫星设计和制造电子产品的“新空间”公司是主要目标客户，而在极端热环境中工作的非辐射加固应用，如航空和石油/天然气钻井的“井下”电子产品，也是该技术的目标市场。该小型企业技术转移研究（STTR）第一阶段项目旨在证明创新的可行性，以有效解决在空间应用所需的扩展温度范围内运行的互连（IC）封装的可靠性挑战。有许多未知数和技术挑战需要探索，需要广泛的跨学科研究和开发。我们的目标是找到一种解决方案，有效地消除热膨胀引起的机械应力，同时具有可接受的热和电气性能，特别是在大功率IC中，如功率转换器/稳压器。该研究将确定该结构对底层硅施加的应力水平，以及在对底层硅芯片造成损坏之前允许的应力水平。 该项目还将评估与温度循环相关的可靠性/风险，并评估最适合满足技术需求的材料，同时提供具有成本效益的可制造解决方案。 该团队将调查现有商业制造工艺的适用性，以及其中的修改如何影响其可制造性。 他们还将研究可能的几何增强以减少屈曲，探索各种几何形状和结构组成中的应力缓解与热阻权衡，该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查进行评估，被认为值得支持的搜索.

The broader impact/commercial potential of this Small Business Technology Transfer Research (STTR) Phase I project seeks to enable cost effective, compact, and higher performing integrated circuits for space applications. Space electronics have lagged the commercial state-of-the-art by over a decade. The lack of high performing, cost effective packaging solutions further increases this gap. Traditionally, space applications utilize large, expensive, and low-performing ceramic packages that limit adoption of radiation-hardened semiconductors into the “New Space” applications such as Low Earth Orbit (LEO) mega-constellations for worldwide internet. “New Space” companies that design and manufacture electronics for satellites are the primary target customers while non-radiation-hardened applications that behave in extreme thermal environments, such as aviation and “down borehole" electronics for the oil/gas drilling, are also a target market for the technology. This Small Business Technology Transfer Research (STTR) Phase I project seeks to prove the feasibility of the innovation to effectively address the reliability challenges in interconnect (IC) packages operating over the extended temperature ranges required in space applications. There are multiple unknowns and technical challenges to be explored, requiring extensive interdisciplinary research and development. The goal is to arrive at a solution that effectively alleviates the mechanical stresses caused by the thermal expansion, while having acceptable thermal and electrical performance, particularly in high-power ICs, such as power converters/regulators. The research will determine the level of stress applied by the structure to the underlying silicon and the level of stress that is permitted before damage to the underlying silicon die will occur. The project will also assess the reliability/risks associated with the temperature cycling and evaluate materials that are best suited to address the technical needs, while also offering a cost-effective manufacturable solution. The team will investigate the suitability of existing commercial fabrication processes and how modifications in them may impact their manufacturability. They will also investigate possible geometry enhancements to reduce buckling, explore the stress-alleviation versus thermal resistance tradeoffs in various geometries and compositions of structures, and create models that support design guidelines for optimal placement of sensitive circuits on the die.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.