EAGER: Transforming Optical Neural Network Accelerators with Stochastic Computing

EAGER：利用随机计算改造光神经网络加速器

• 批准号: 2139167
• 负责人: Ishan Thakkar
• 金额: $ 29.97万
• 依托单位: University of Kentucky Research Foundation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2021
• 资助国家: 美国
• 起止时间: 2021-10-01 至 2024-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2139167&HistoricalAwards=false
• 关键词: EAGER; Transforming; Optical; Neural; Network

In the past decade, machine learning algorithms and models such as Deep Neural Networks (DNNs) have become increasingly prevalent for many emerging applications, such as medical prognosis, autonomous transportation, weather forecast, speech recognition and translation, image/video recognition and synthesis. This increasing prevalence has necessitated that the computing hardware platforms that process DNNs deliver consistently high performance and fast processing speeds. This need has driven computer hardware architects to design custom accelerator chips for processing DNNs. As researchers explore more sophisticated and powerful models of DNNs, the compute speed and throughput requirements from these DNN accelerator chips also increase. Traditional electronic implementations of DNN accelerator chips are breaking down under this pressure, which is catastrophic as it prevents the immediate widespread adoption of high-performance artificial intelligence that can transform society and improve lives. Fortunately, silicon photonics-based optical computing (OC) has emerged as an exciting paradigm that can replace slow electronic processing of DNNs with much faster, light-speed DNN processing. By processing DNNs directly in the optical domain, OC-based DNN accelerator chips have the potential to provide up to a thousand times faster processing speeds than traditional electronic chips. However, viable realization and deployment of OC-based DNN accelerators present enormous challenges, because the silicon-photonic building blocks of such accelerators consume very high static power, require excessively large silicon real estate, exhibit susceptibility to uncertainty induced errors, and lack flexibility. This project will involve transformative research to overcome these fundamental challenges and pave the way for realizing future OC-based DNN accelerator chips that are miniature in size, but possess the computing power to enable lower-cost, ultra-fast, and highly reliable processing of artificial intelligence tasks. Close collaborations with academic partners at the NSF NNCI node, Kentucky Multiscale, will aid in the rapid prototyping of the developed technology. The key contribution of this project will be to design potentially groundbreaking architectures of OC-based DNN accelerators that will employ stochastic computing (SC) to realize various DNN processing functions. This project is critical early exploratory research because it focuses on a radically transformative goal of merging the disciplines of SC and OC in a highly synergistic manner for the important use case of DNN accelerator design. Such synergistic integration of SC and OC has never been explored before and involves interdisciplinary perspectives and new approaches that are considered to be more “high risk-high payoff” than the typical research in CSR or other areas of CISE/NSF. The proposed synergistic integration of SC and OC will lay down a blueprint for realizing a new class of DNN accelerator architectures that will combine the processing speed benefits of OC with the area-efficiency, flexibility, static power efficiency, and error tolerance of SC, and be at the heart of the revolutionary artificial intelligence of the next generation to transform our lives in innumerable ways. Moreover, by exposing graduate students to the diverse aspects of stochastic arithmetic, probability theory, optical computing, nanofabrication, deep neural networks, and electro-optical characterization, this project will contribute towards an agile, high-tech workforce that will maintain continued US leadership in technological innovation.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

在过去的十年中，机器学习算法和模型（如深度神经网络（DNN））在许多新兴应用中变得越来越普遍，如医疗预后，自主交通，天气预报，语音识别和翻译，图像/视频识别和合成。这种日益普及的趋势使得处理DNN的计算硬件平台必须提供始终如一的高性能和快速处理速度。这种需求促使计算机硬件架构师设计用于处理DNN的自定义加速器芯片。随着研究人员探索更复杂和强大的DNN模型，这些DNN加速器芯片的计算速度和吞吐量要求也会增加。DNN加速器芯片的传统电子实现在这种压力下正在崩溃，这是灾难性的，因为它阻止了可以改变社会和改善生活的高性能人工智能的立即广泛采用。幸运的是，基于硅光子学的光学计算（OC）已经成为一种令人兴奋的范例，可以用更快的光速DNN处理来取代DNN的缓慢电子处理。通过直接在光域中处理DNN，基于OC的DNN加速器芯片有可能提供比传统电子芯片快上千倍的处理速度。然而，基于OC的DNN加速器的可行实现和部署提出了巨大的挑战，因为这种加速器的硅光子构建块消耗非常高的静态功率，需要过大的硅真实的资产，表现出对不确定性引起的误差的敏感性，并且缺乏灵活性。该项目将涉及变革性研究，以克服这些根本性挑战，并为实现未来基于OC的DNN加速器芯片铺平道路，这些芯片尺寸微小，但具有计算能力，可以实现低成本，超快速和高度可靠的人工智能任务处理。与NSF NNCI节点肯塔基州Multiscale的学术合作伙伴密切合作，将有助于开发技术的快速原型。该项目的主要贡献将是设计基于OC的DNN加速器的潜在突破性架构，该架构将采用随机计算（SC）来实现各种DNN处理功能。该项目是关键的早期探索性研究，因为它专注于以高度协同的方式合并SC和OC学科的根本变革目标，用于DNN加速器设计的重要用例。这种SC和OC的协同整合以前从未被探索过，涉及跨学科的观点和新的方法，被认为是比CSR或CISE/NSF其他领域的典型研究更“高风险，高回报”。SC和OC的协同集成将为实现新型DNN加速器架构奠定蓝图，该架构将联合收割机的处理速度优势与SC的面积效率，灵活性，静态功率效率和容错能力相结合，并成为下一代革命性人工智能的核心，以无数方式改变我们的生活。此外，通过让研究生接触随机算术，概率论，光学计算，纳米纤维，深度神经网络和电光表征的各个方面，该项目将有助于实现敏捷，表示“高”之义该奖项反映了NSF的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准。

项目成果

An Optical XNOR-Bitcount Based Accelerator for Efficient Inference of Binary Neural Networks

• DOI: 10.1109/isqed57927.2023.10129294
• 发表时间: 2023-02
• 期刊: 2023 24th International Symposium on Quality Electronic Design (ISQED)
• 作者: Sairam Sri Vatsavai;Venkata Sai Praneeth Karempudi;Ishan G. Thakkar

AGNI: In-Situ, Iso-Latency Stochastic-to-Binary Number Conversion for In-DRAM Deep Learning

• DOI: 10.1109/isqed57927.2023.10129301
• 发表时间: 2023-02
• 期刊: 2023 24th International Symposium on Quality Electronic Design (ISQED)
• 作者: Supreeth Mysore Shivanandamurthy;Sairam Sri Vatsavai;Ishan G. Thakkar;S. A. Salehi

High-Speed and Energy-Efficient Non-Binary Computing with Polymorphic Electro-Optic Circuits and Architectures

• DOI: 10.1145/3583781.3590258
• 发表时间: 2023-04
• 期刊: Proceedings of the Great Lakes Symposium on VLSI 2023
• 作者: Ishan G. Thakkar;Sairam Sri Vatsavai;Venkata Sai Praneeth Karempudi

Photonic Reconfigurable Accelerators for Efficient Inference of CNNs With Mixed-Sized Tensors

• DOI: 10.1109/tcad.2022.3197538
• 发表时间: 2022-07
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Sairam Sri Vatsavai;Ishan G. Thakkar

A Bit-Parallel Deterministic Stochastic Multiplier

位并行确定性随机乘法器

• DOI: 10.1109/isqed57927.2023.10129297
• 发表时间: 2023
• 期刊: IEEE International Symposium on Quality Electronic Design
• 作者: Vatsavai, Sairam Sri;Thakkar, Ishan
• 通讯作者: Thakkar, Ishan