CAREER: Reliability of Three-dimensional Interconnects for Heterogeneous Integration: An Integrated Experimental and Modeling Study

职业：异构集成三维互连的可靠性：综合实验和建模研究

• 批准号: 2144033
• 负责人: Tengfei Jiang
• 金额: $ 50万
• 依托单位: The University of Central Florida Board of Trustees
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2022
• 资助国家: 美国
• 起止时间: 2022-03-01 至 2027-02-28
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2144033&HistoricalAwards=false
• 关键词: CAREER; Reliability; Three; dimensional; Interconnects

Three-dimensional integrated circuits (3DIC), where chips are vertically connected by through-substrate vias, is one of the most promising technologies to overcome the materials and processing limitations of Moore’s Law Scaling. This project aims to develop fundamental knowledge and practical solutions to address the critical reliability challenges for the integration and scaling of high density through-substrate vias in 3D heterogeneous integration. Using a combined experimental and modeling approach, the proposed work will study the 3D interconnect system of current interest, namely copper (Cu) through-silicon vias (TSVs), to elucidate the effect of stress, microstructure, and scaling on the deformation and failure mechanisms, model the effect of dimensional scaling on microstructure evolution, device performance and reliability, and develop an innovative solution to control via protrusion and enable reliable 3D interconnects. By solving these critical challenges, this research will generate new knowledges in the reliability of 3D interconnects to enable high density 3D heterogeneous integration, which is critical for a broad range of applications such as high-performance computing, autonomous vehicles, mobile connectivity, and aerospace and defense applications. This project also entails educational and outreach activities aiming at educating and training talents in interconnect reliability to advance America’s scientific and technological leadership in microelectronics technology.The objective of this project is to develop an integrated research program that combines experiments and modeling to address the reliability challenges of three-dimensional (3D) interconnects, which are essential for vertical heterogeneous chip-package integration. Using copper (Cu) through-silicon via (TSV) and via protrusion as a model system, this project will address the important knowledge gaps in the reliability for 3D interconnects, including: 1) establish the quantitative correlation between the microstructure and deformation, which will lead to the identification of critical microstructure features and deformation mechanisms that dictate the high tail of the reliability statistics; 2) determine the effect of scaling on microstructure evolution, device performance and the resulting reliability statistics, which is particularly important for the development of high-density heterogeneous integration; 3) develop methods to control the reliability statistics using approaches based on materials and interface optimization. The fundamental knowledges, practical solutions, and methodologies generated in this work will be appliable to other metallization and substrate systems beyond Cu TSVs. By enabling 3D heterogeneous integration, this project will pave the way for many key applications ranging from mobile devices and consumer electronics to medical devices and autonomous vehicles. The educational component of this project will integrate classroom teaching, research training, and outreach activities to inspire, educate and train students, with special attention to women and underrepresented minority student groups, and will produce talented workforce in interconnect reliability at one of the nation’s largest universities by enrollment to help US’s microelectronics industry retain its competitiveness and global leadership.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

三维集成电路（3DIC）是克服摩尔定律缩放的材料和工艺限制的最有前途的技术之一，其中芯片通过穿过衬底的通孔垂直连接。该项目旨在开发基础知识和实用解决方案，以解决3D异构集成中高密度基板通孔集成和缩放的关键可靠性挑战。采用实验和建模相结合的方法，本研究将研究当前感兴趣的三维互连系统，即铜（Cu）通硅过孔（tsv），以阐明应力，微观结构和缩放对变形和破坏机制的影响，模拟尺寸缩放对微观结构演变，器件性能和可靠性的影响，并开发一种创新的解决方案，通过突出控制和实现可靠的三维互连。通过解决这些关键挑战，该研究将产生3D互连可靠性方面的新知识，以实现高密度3D异构集成，这对于高性能计算，自动驾驶汽车，移动连接以及航空航天和国防应用等广泛应用至关重要。该项目还包括教育和推广活动，旨在教育和培训互连可靠性方面的人才，以推动美国在微电子技术方面的科技领先地位。该项目的目标是开发一个综合研究计划，将实验和建模相结合，以解决三维（3D）互连的可靠性挑战，这对于垂直异构芯片封装集成至关重要。以铜（Cu）通硅通孔（TSV）和通孔突出为模型系统，本项目将解决三维互连可靠性方面的重要知识空白，包括：1)建立微观结构与变形之间的定量相关性，从而确定决定可靠性统计高尾的关键微观结构特征和变形机制；2)确定尺度对微观结构演变、器件性能和由此产生的可靠性统计的影响，这对高密度异构集成的发展尤为重要；3)开发基于材料和界面优化的可靠性统计控制方法。在这项工作中产生的基本知识、实际解决方案和方法将适用于Cu tsv以外的其他金属化和衬底系统。通过实现3D异构集成，该项目将为从移动设备和消费电子产品到医疗设备和自动驾驶汽车的许多关键应用铺平道路。该项目的教育部分将整合课堂教学，研究培训和外展活动，以激励，教育和培训学生，特别关注女性和代表性不足的少数民族学生群体，并将在美国最大的大学之一培养互连可靠性方面的人才，以帮助美国微电子工业保持竞争力和全球领导地位。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。