Dynamically reconfigurable filters for digital signal processing with integrated circuits

用于使用集成电路进行数字信号处理的动态可重构滤波器

• 批准号: 250645438
• 负责人: Professor Dr.-Ing. Peter Zipf
• 金额: --
• 依托单位: Fachgebiet Digitaltechnik
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2014
• 资助国家: 德国
• 起止时间: 2013-12-31 至 2017-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/250645438?language=en
• 关键词: Dynamically; reconfigurable; filters; digital; signal

The goal of the proposed project is the development of optimization techniques for architectures to realize dynamically reconfigurable filters for digital signal processing. Dynamic reconfiguration allows to change the properties of filters during runtime. Such specialized filters are essential to cope with the rising complexity of advanced applications in information and communication technologies as well as advanced control applications. Having the possibility to adjust the requirements during runtime makes the use of dynamically reconfigurable filters more advantageous in comparison to conventional digital filters. Besides the decrease in complexity, a decrease in device costs and power consumption plays a major role. These design goals can be reached by applying the computer aided optimization of dynamically reconfigurable filters for freely programmable logic i.e. field programmable gate arrays (FPGAs), e.g. by the possibility of shared utilization of FPGA components, covered by the project. In this context both dynamic reconfiguration of logic by reconfigurable look-up tables and dynamic reconfiguration of the routing by multiplexers shall be optimized. Partial reconfiguration (PR) in Xilinx FPGAs will be applied in order to make comparisons. The destinated goal is to be able to generate optimized implementations of reconfigurable filters (concerning the requirements power consumtion, costs and performance) which can be used in future applications of digital signal processing and which extend the state of the art. The approaches to solution should be applicable for FPGAs and besides this for VLSI implementations in general.

该项目的目标是开发用于数字信号处理的动态可重构滤波器的结构优化技术。动态重新配置允许在运行时更改过滤器的属性。这种专用滤波器对于科普信息和通信技术中的高级应用以及高级控制应用的日益复杂性至关重要。与传统数字滤波器相比，在运行时调整要求的可能性使得动态可重配置滤波器的使用更加有利。除了复杂性的降低之外，设备成本和功耗的降低也起着重要作用。这些设计目标可以通过对可自由编程逻辑（即现场可编程门阵列（FPGA））的动态可重新配置滤波器进行计算机辅助优化来实现，例如，通过该项目所涵盖的FPGA组件的共享利用的可能性。在这种情况下，通过可重新配置的查找表进行的逻辑的动态重新配置和通过多路复用器进行的路由的动态重新配置都将被优化。为了进行比较，将在Xilinx FPGA中应用部分重新配置（PR）。我们的目标是能够产生可重构滤波器的优化实现（关于功耗，成本和性能的要求），可用于未来的数字信号处理的应用程序，并扩展了最先进的解决方案的方法应该适用于FPGA和除此之外的VLSI实现一般。