ITR: Optimization of Reconfigurable Architectures for Efficient Implementation of Particle Filters

粒子滤波器的可重构结构优化近年来，粒子滤波器在许多研究领域引起了极大的关注。这些滤波器用于必须在真实的时间中处理时变信号的问题中，其目的是估计信号的各种未知数并检测由信号描述的事件。在许多应用中，这些问题的标准解决方案是基于卡尔曼或扩展卡尔曼滤波器。在问题高度非线性或使信号失真的噪声是非高斯的情况下，卡尔曼滤波器提供的解决方案可能远非最佳。 粒子滤波器的一个主要缺点是它们的实现在计算上非常密集。然而，它们本质上是可并行的，并且可以为它们的实现构建特殊的硬件，以满足实时处理的严格要求。在这项研究中，可重构和物理上可行的粒子滤波器的VLSI架构的发展。在这些体系结构的发展过程中，许多重要的问题被研究。其中最关键的是硬件和软件的平衡，这本身与其他重要问题密切相关。它们包括减少计算复杂性的转换和近似，调查的并行度实施的过滤器，调查的各种互连机制，随机通信方案，硬件优化和低功耗VLSI处理器的设计。这项工作还包括构建可重构硬件，以便适用于不同类型的粒子滤波器。

ABSTRACT0220011Djuric, PetarSUNY @ Stony BrookOptimization of Reconfigurable Architectures for Efficient Implementation of Particle FiltersIn recent years particle filters have attracted great attention in several research communities. These filters are used in problems where time-varying signals must be processed in real time and the objective is to estimate various unknowns of the signals and to detect events described by the signals. The standard solutions of such problems in many applications are based on the Kalman or extended Kalman filters. In situations when the problems are highly nonlinear or the noise that distorts the signals is non-Gaussian, the Kalman filters provide solutions that may be far from optimal. A major drawback of the particle filters is that their implementation is computationally very intensive. They are, however, inherently parallelizable, and special hardware can be built for their implementation that can meet the stringent requirements of real-time processing. In this research, reconfigurable and physically feasible VLSI architectures for particle filters are developed. In the development of these architectures, many important problems are researched. The most critical of them is the balancing of hardware and software, which itself is tightly related to other important issues. They include reductions of computational complexities by transformations and approximations, investigation of the degree of parallelism implemented in the filter, investigation of various interconnection mechanisms, random communication schemes, hardware optimization, and design of low power VLSI processors. This effort also includes building of reconfigurable hardware so that it is suitable for different types of particle filters.