Excellence in Research: Improving the Integrity and Security of Integrated Circuits Through Effective Detection of Malicious Alterations

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In today’s information age every aspect of our lives depends on technology. In the core of the hardware that runs this technology is the integrated circuit (IC). While integrated circuits (ICs) are ubiquitously deployed in modern electronic/information systems that process critical data in our daily lives, the design and fabrication of these ICs however are becoming increasingly vulnerable to malicious activities and alterations due to the globalization of electronic design supply chain (i.e., most of the ICs used in electronic systems are now fabricated outside the United States). An adversary (untrusted foundry) could potentially subvert the fabrication process itself by implanting a hardware Trojan into the IC mask to disable and/or destroy a system at some future time or the Trojan may serve to leak confidential/sensitive information covertly to the adversary. Today, Trojans can be cleverly hidden by the adversary to make it extremely difficult for chip test/validation processes (since the adversary has complete access to test information as manufacturing tests are typically performed at the chip fabrication site). These vulnerabilities have raised serious concerns regarding possible threats to many critical systems including military, financial, telecommunications, energy, and transportation infrastructures. The focus of this project is to define a post-manufacturing test step (prior to electronics system integration) to increase trustworthiness of the ICs fabricated at offshore facilities to validate the conformance of the chip with its original functionality and performance specification. Specifically, this project will analyze circuit delays as a method to detect and locate hardware Trojans and develop novel methods such as clock frequency sweeping for targeting Trojans in presence of process variations. To increase efficiency, the planned research activity will be to develop an on-chip measurement technique to target paths missed or short paths not testable by the clock sweeping method to detect Trojans. This proposed two complementary approaches will effectively detect and localize all types of hardware Trojans. Other planned research activities include implementation of different types of hardware Trojans on field programmable gate arrays (FPGAs) and development of statistical analysis methods for the collected silicon data.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.