Collaborative Research: Integrated Sensing and Normally-off Computing for Edge Imaging Systems

到2025年，物联网(IoT)设备预计将超过1000亿美元，预计互联网络将包含约750亿台IoT设备。大量的物联网由感官成像系统组成，这些系统能够从环境和人类中收集大量数据。然而，捕获的感官数据中有相当一部分是冗余的和非结构化的。如此大的原始数据的数据转换，存储在易失性存储器中，在片上/片外处理器中进行传输和计算，造成了高能量消耗、延迟和边缘的存储器瓶颈。此外，由于为物联网设备更换电池非常昂贵，有时甚至是不可行的，因此具有环境能源和低维护成本的能量收集设备已经影响了可穿戴设备、智能城市和智能行业等广泛的物联网应用。该项目探索和设计了新的高速、低功耗和正常关闭的计算体系结构，用于资源有限的感官节点，利用跨层后CMOS方法来克服这些问题。这项研究的成功完成将使各种关键应用领域受益，包括医疗监测、工业和/或环境传感器。该项目将大力开发本科生和研究生课程模块，宣传可移植和开放源码的模式，并通过出版物/在知识传播会议上的演讲扩大STEM的参与。推力1号设计和分析了一个传感器内处理单元(PISU)，它将始终在线的传感和处理能力与近距离处理传感器单元(PNSU)结合在一起。该混合平台将采用实时可编程的粒度可配置算术运算，以在连续成像和能量采集供电的成像场景下平衡精度、速度和能效之间的权衡。该平台将使资源有限的边缘设备能够在本地执行数据和计算密集型应用，如机器学习任务，同时消耗的电力比目前最先进的技术低得多。环境能源的功率分布对加工稳定性和持续时间施加了基本限制。为了在不稳定的电源条件下实现高的传感和计算并行性，将设计间歇-稳健集成传感计算(IRISC)。在停电期间，IRISC将中间值存储在基于自旋的非易失性设备中，这将确保不间断运行。为了满足硬件限制并缓解基于自旋的设备的高写入功率，它们将通过一种新颖的NV集群方法被选择性地高效地插入到数据路径中，以创建相应的间歇健壮IP核，在保持中间件一致性的同时以较低的功耗实现间歇计算。这种跨层的设备到系统研究方法将通过为IRIS开发一个全面的评估框架、一个可传输的能量采集计算工作负载套件和基于FPGA-MRAM的仿真平台进行评估。该奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

Internet of Things (IoT) devices are projected to exceed $1000B by 2025, with a web of interconnection projected to comprise approximately 75+ billion IoT devices. The large number of IoTs consists of sensory imaging systems that enable massive data collection from the environment and people. However, considerable portions of the captured sensory data are redundant and unstructured. Data conversion of such large raw data, storing in volatile memories, transmission, and computation in on-/off-chip processors, impose high energy consumption, latency, and a memory bottleneck at the edge. Moreover, because renewing batteries for IoT devices is very costly and sometimes impracticable, energy harvesting devices with ambient energy sources and low maintenance have impacted a wide range of IoT applications such as wearable devices, smart cities, and the intelligent industry. This project explores and designs new high-speed, low-power, and normally-off computing architectures for resource-limited sensory nodes by exploiting cross-layer post-CMOS approaches to overcome these issues. Successful completion of this research will have benefits to a variety of critical application domains, including medical monitoring, industrial and/or environmental sensors. This project will make a strong effort on developing undergraduate and graduate course modules, propagating transportable and open-source models, and broadening STEM participation through publications/presentations at conferences for knowledge dissemination.This project will follow two main research thrusts. Thrust 1 designs and analyzes a Processing-In-Sensor Unit (PISU) co-integrating always-on sensing and processing capabilities in conjunction with a Processing-Near-Sensor Unit (PNSU). The hybrid platform will feature real-time programmable granularity-configurable arithmetic operations to balance the accuracy, speed, and power-efficiency trade-offs under both continuous and energy-harvesting-powered imaging scenarios. This platform will enable resource-limited edge devices to locally perform data and compute-intensive applications such as machine learning tasks while consuming much less power than present state-of-the-art technology. The power profile of ambient energy sources imposes fundamental constraints on processing stability and duration. To achieve high sensing and computation parallelism under unstable power supply conditions, Intermittent-Robust Integrated Sensing Computation (IRISC) will be designed. During power failure, IRISC stores intermediate values in non-volatile spin-based devices, which will ensure uninterrupted operations. To meet the hardware constraints and mitigate the high write power of spin-based devices, they will be selectively and efficiently inserted within the datapaths through a novel NV-clustering methodology to create corresponding intermittent-robust IP cores that realize intermittent computation with lower power consumption while maintaining middleware coherence. This cross-layer devices-to-system research approach will be assessed by developing a comprehensive evaluation framework, a transportable energy-harvested computational workload suite, and FPGA-MRAM-based emulation platforms for IRISC.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.