Collaborative Research: SaTC: CORE: Medium: Hardware Security Insights: Analyzing Hardware Designs to Understand and Assess Security Weaknesses and Vulnerabilities

该项目的目标是开发更好的方法来了解计算机硬件设计中的信息流动，从而提高它们的安全性。所有计算设备核心的微处理器、无线调制解调器、图形处理单元和其他硬件组件都是由工程师使用低级硬件描述语言设计的。这些设计很复杂，因此很难对安全漏洞进行推理，这些漏洞可能会让攻击者提取有价值的秘密信息，如加密密钥和个人身份信息。硬件安全验证的目的是识别硬件弱点，修补潜在的漏洞，减轻攻击的危害。了解硬件设计中的信息流可以帮助验证工程师评估攻击者是否可以提取机密数据，并开发防止这些易受攻击的流的设计。该项目围绕三个主要目标构建，共同带来有关硬件信息流跟踪的改进工具。第一个目标是自动生成信息流属性，然后可以通过现有工具进行验证。第二是开发测试台，通过设计充分行使可能的信息流，使用天使般的执行神谕，旨在最大限度地覆盖可能的信息流。三是开发一种新的“超流分析”框架，既提供支持硬件设计和验证算法的解析表示，又提供帮助验证工程师通过信息流透镜探索硬件漏洞的可视化表示。这项工作将涉及一些本科生和研究生，为计算机安全工作队伍的发展做出贡献。这一奖项反映了NSF的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

This project’s goal is to develop better methods for understanding how information flows in computer hardware designs, and thus increase their security. The microprocessors, wireless modems, graphics processing units, and other hardware components at the heart of all computing devices are designed by engineers using low-level hardware description languages. These designs are complex, making it difficult to reason about security vulnerabilities that may allow attackers to extract valuable secret information like cryptographic keys and personally identifiable information. Hardware security verification aims to identify hardware weaknesses, patch potential vulnerabilities, and mitigate the harm of attacks. Understanding how information flows in hardware designs can help verification engineers to assess whether secret data can be extracted by an attacker and to develop designs that prevent those vulnerable flows.The project is structured around three main aims that together will lead to improved tools for insights around hardware information flow tracking. The first aim is to automate the generation of information-flow properties, which can then be verified by existing tools. The second is to develop testbenches that fully exercise possible information flows through a design, using angelic execution oracles designed to maximize coverage of possible information flows. The third is to develop a new “hyperflow analysis” framework that provides both analytic representations to support algorithms for hardware design and verification, and visual representations that help verification engineers explore hardware vulnerabilities through an information-flow lens. The work will involve a number of undergraduate and graduate students, contributing to the development of the computer security workforce.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.