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CAREER: Scalable Physics-Inspired Ising Computing for Combinatorial Optimizations

CAREER: Scalable Physics-Inspired Ising Computing for Combinatorial Optimizations
职业:用于组合优化的可扩展物理启发伊辛计算
批准号:
2340453
负责人:
Bongjin Kim
金额:
$58.91万
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2024
资助国家:
美国
项目状态:
未结题
起止时间:
2024-01-01 至 2028-12-31

项目摘要

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中文摘要
翻译
伊辛计算是受原子自旋间的铁磁性自然物理现象启发而提出的一种计算范式。在这种非传统的计算方法中,组织在图形中的人工自旋动态地相互作用,推动系统快速收敛到最小能量状态-最优解的表示。利用这种收敛行为的伊辛计算机与经典计算机相比表现出指数加速,特别是在解决物流、制造、供应链管理、药物发现和金融投资组合优化等不同领域的复杂优化问题方面表现出色。尽管正在努力开发使用经典和新兴技术的伊辛计算机,但没有一个有效地解决了与可扩展性,可重新配置性和连接性相关的关键挑战-实现实用的伊辛计算解决方案的基本因素。该项目旨在通过构建混合信号和数字专用集成电路(ASIC)硬件加速器来应对这些挑战。 该项目将通过在大学引入新的本科生和研究生课程来整合研究和教育,通过提供集成电路设计实践项目的机会,从而解决半导体行业急需的国家劳动力发展问题,例如,该项目的具体方法分为三个关键领域。首先,最初的方法旨在通过实现具有较少局部自旋交互的许多物理自旋来解决可扩展性挑战。这涉及到在混合信号Ising计算机中集成紧凑的锁存电路,提供一个大规模的Ising计算机,而不需要片外随机数发生器,这是解决大规模组合优化问题的关键特征。除了可扩展性之外,该方法还旨在通过连续时间操作利用大规模并行性来大幅减少计算延迟。第二种方法将实现一个灵活的数字伊辛计算机,以解决硬件开销的问题,这来自于映射复杂的问题,以更简单的互连在一个规则的网格拓扑结构,如点阵图的伊辛计算机。灵活的伊辛计算机旨在融合空间和时间(时空)自旋连接,以实现最大的可重构性,从而最大限度地减少硬件开销。由此产生的伊辛计算机与灵活的时空之间的相互作用的自旋预计将显着减少所需的物理自旋的数量和提高精度。最后,该项目的目标是实现一个具有全对全自旋互连的内存中伊辛计算机,通过将自旋嵌入内存阵列中,通过一个庞大的交换机网络互连,来解决连接性挑战。这种方法旨在增强连接性和简化自旋相互作用,有助于提高伊辛计算机的整体效率和有效性。该奖项反映了NSF的法定使命,并通过使用基金会的知识价值和更广泛的影响审查标准进行评估,被认为值得支持。
英文摘要
Ising computing is an alternative computing paradigm inspired by the natural physical phenomena of ferromagnetism among atomic spins. In this unconventional computing approach, artificial spins organized in a graph dynamically interact, propelling the system toward rapid convergence to the minimum energy state – a representation of the optimal solution. The Ising computer, leveraging such convergence behavior, exhibits exponential acceleration compared to classical counterparts, particularly excelling in solving intricate optimization problems across diverse sectors such as logistics, manufacturing, supply chain management, drug discovery, and financial portfolio optimization. Despite ongoing efforts to develop Ising computers using classical and emerging technologies, none have effectively addressed critical challenges related to scalability, reconfigurability, and connectivity – essential factors for realizing practical Ising computing solutions. This project aims to tackle these challenges by constructing mixed-signal and digital application-specific integrated circuit (ASIC) hardware accelerators. The project will integrate research and education by introducing new undergraduate and graduate level courses at the university, by providing opportunity to work on hands-on projects on integrated circuit design, thus addressing a much-needed national workforce development for the Semiconductor Industry as, e.g., articulated in the recent Chips and Science Act.The specific approaches of the project are categorized into three key areas. Firstly, the initial approach aims to tackle scalability challenges by implementing many physical spins with fewer local spin interactions. This involves integrating compact latch circuits in a mixed-signal Ising computer, providing a large-scale Ising computer without the need for off-chip random number generators, which is a crucial feature for addressing large-scale combinatorial optimization problems. Beyond the scalability, the approach also aims to substantially reduce computing latency by leveraging massive parallelism through continuous-time operation. The second approach will implement a flexible digital Ising computer to address the issue of hardware overhead, which comes from mapping complex problems to the Ising computer with simpler interconnects in a regular grid topology, such as a lattice graph. The flexible Ising computer aims to amalgamate spatial and temporal (spatio-temporal) spin connectivity to achieve maximum reconfigurability, thereby minimizing hardware overhead. The resulting Ising computer with flexible spatio-temporal interactions between spins is anticipated to significantly reduce the required number of physical spins and enhance accuracy. Lastly, this project aims to implement an in-memory Ising computer with all-to-all spin interconnects to address connectivity challenges by embedding spins in the memory array, interconnected via a massive network of switches. This approach is designed to enhance connectivity and streamline spin interactions, contributing to the overall efficiency and effectiveness of the Ising computer.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.
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Scalable Learning and Optimization: High-dimensional Models and Online Decision-Making Strategies for Big Data Analysis