CAREER: HeteroTime: Accelerating Static Timing Analysis with Intelligent Heterogeneous Parallelism

该奖项的全部或部分资金均根据《2021 年美国救援计划法案》（公法 117-2）提供。随着设计复杂性持续呈指数级增长，高效分析大型硬件设计时序的需求已成为设计收敛流程的主要瓶颈。为了减少长时间的分析运行时间，近年来出现了许多并行静态时序分析（STA）解决方案。尽管性能有所提高，但一个关键的基本挑战仍未得到解决：几乎所有现有的并行 STA 解决方案在架构上都受到中央处理单元 (CPU) 并行性的限制，并且其可扩展性结果在 8 到 16 个 CPU 核心时基本上停滞不前。下一代处理技术将具有更复杂的分析场景，从而导致更高数量级的计算复杂性，远远超出现有 CPU 并行 STA 解决方案的扩展能力。因此，加速 STA 算法是电子设计自动化 (EDA) 工具的一个高度研究重点，以提高设计收敛流程的性能。该 CAREER 项目创建了一种新颖的开源 STA 引擎，该引擎 1) 通过利用异构计算和机器学习的力量实现变革性的性能突破，2) 为研究人员建立一个开放平台，为设计自动化研究和教育做出贡献。拟议的研究和教育活动将促进技术转让并实现多样化的产学合作。该 CAREER 项目研究新颖的 STA 算法，通过利用异构并行性和机器学习的力量，实现数量级的性能突破。它将研究新颖的图形处理单元（GPU）内核算法和异构任务分解策略，以从新颖的计算角度加速关键的STA问题，包括基于图的分析和基于路径的分析。此外，它将建立一个基于学习的任务执行环境，以实现在实际操作条件下针对不同STA工作负载的自适应性能优化。研究成果将实现超越当前最先进技术的超快速分析和优化算法，并显着提高设计收敛流程的周转时间和结果质量 (QoR)。该项目的技术贡献将跨越多学科研究社区，包括 EDA、并行计算、机器学习和图形算法。该项目的结果将开源，以鼓励广泛的 EDA 研究人员和开发人员通过分享新的发现、想法和教育资源为该项目做出贡献。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

This award is funded in whole or in part under the American Rescue Plan Act of 2021 (Public Law 117-2).As design complexity continues to grow exponentially, the need to efficiently analyze the timing of large hardware designs has become the major bottleneck to the design closure flow. To reduce long analysis runtimes, recent years have seen many parallel static timing analysis (STA) solutions. Despite improved performance, a key fundamental challenge remains unsolved: Almost all existing parallel STA solutions are architecturally constrained by central processing unit (CPU) parallelism, and their scalability results largely plateaued at 8 to 16 CPU cores. Next-generation process technologies will feature more complex scenarios to analyze, resulting in order-of-magnitude higher computational complexity that far exceeds what existing CPU-parallel STA solutions can scale to. Speeding up STA algorithms is thus a high research priority for electronic design automation (EDA) tools to boost the performance of design closure flows. This CAREER project creates a novel open-source STA engine that 1) delivers transformational performance breakthroughs by harnessing the power of heterogeneous computing and machine learning and 2) establishes an open platform for researchers to contribute to design automation research and education. The proposed research and education activities will facilitate technology transfers and enable diverse industry-academia collaborations.This CAREER project researches novel STA algorithms that deliver order-of-magnitude performance breakthroughs by harnessing the power of heterogeneous parallelism and machine learning. It will research novel graphics processing unit (GPU) kernel algorithms and heterogeneous task decomposition strategies to accelerate critical STA problems, including graph-based analysis and path-based analysis, from a novel computing perspective. Furthermore, it will establish a learning-based task execution environment to achieve adaptive performance optimization to different STA workloads under real operating conditions. The research outcomes will enable ultra-fast analysis and optimization algorithms over the current state-of-the-art and substantially improve both turnaround time and quality of results (QoR) for design closure flows. Technical contributions of this project will span a multidisciplinary research community, including EDA, parallel computing, machine learning, and graph algorithms. Results of the project will be made open-source to encourage a wide range of EDA researchers and developers to contribute to the project by sharing new findings, ideas, and educational resources.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.