Synergistic Integration of Novel Superconductor Electronics for Energy-Efficient Computing Accelerators

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In this year we investigated the co-integration of different superconductor logic families in a hybrid manner. We developed a standard cell layout architecture for building hybrid AC/DC-biased logic circuits (10.1109/TASC.2023.3258366). This cell layout architecture is the groundwork in which we can assemble different logic families together on the same chip with appropriate interfacing circuits in a very systematic manner. Next, we developed an demonstrated logic interfacing circuits to exchange data between logic families (10.1109/TASC.2023.3244147). This updated design is more robust compared to previous iterations and even uses a more modern manufacturing process. Then, we developed low-latency hybrid serializers/deserializers (10.1109/ACCESS.2022.3230447). These circuits serve as facilities for data communication between components as well as off-chip transmission. These are excellent examples of synergetic integration between different logic families leveraging their respective strengths. We also looked at important details for scaling up our technology such as issues with signal integrity (10.1109/TASC.2023.3239828) and large-scale clock skew (10.1088/1361-6668/aca3d6). We proposed a candidate architecture for a cryptoprocessor for hybrid integration and demonstrated a major component up to 7 GHz. The work was selected to be featured in Superconductivity News Forum (SNF), Issue No. 52, March 2023.