Performance and Efficiency in HPC with Custom Computing

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Numerous projects have shown that the use of accelerators, such as field-programmable gate arrays (FPGAs), many-core processors, or graphics processing units (GPUs), can provide significant performance and energy-efficiency benefits in high-performance computing. Still, the use of accelerators is not pervasive, even for application domains that are very likely to profit from accelerators. The reasons for the rather slow adoption of accelerators by HPC developers are manifold, for example: lack of technical knowledge about accelerators, unclear value proposition of time investment in code optimization, missing understanding of the optimization potential for applications, lack of suitable training materials, shortage of libraries that allow for reusing accelerators as black boxes. We propose to establish a structured support and consulting process at our compute center, which aims at guiding HPC developers during the complete process from performance analysis and optimization potential estimation to finally optimizing the code by accelerating computationally expensive hotspots. This process enhances teams from computational sciences with complementary expertise and thus adds a value proposition to the performance engineering task by increasing chances to reduce times-to-solution or being able to simulate larger systems. To allow the developers to leverage the experiences and developments from previous work, we will abstract and encapsulate frequently used functions in reusable libraries. Finally, we will develop training materials that are tailored to the needs of developers from computational science and engineering and establish a repository of example codes that illustrate best practices. In this project, we will exploit the specific technological and research strengths of our HPC computing center and our users. First, we leverage the fact that our core HPC users use own and open-source codes and are focused on a small set of application domains (computational nanophotonics, molecular dynamics, quantum chemistry). This focus in application domains allows us to share methods and results for different codes. Second, we will concentrate on FPGAs as accelerator technology, because FPGAs have arguably the highest efficiency potential and also a dynamic market development. The steps towards standardization after the acquisition of Altera by Intel and the introduction of IBM's CAPI accelerator interface, along with improvements of high-level design tools for FPGAs provide a new technological basis for a broader adoption of FPGAs in HPC. We are confident that the combination of our substantial expertise in the area of custom computing with FPGAs and the clear application focus, will allow us to significantly advance the field for high-performance computing with FPGA accelerators and to demonstrate the performance and energy efficiency benefits of FPGAs with actual production HPC codes.