Optimum Capacitor Switching Algorithms For Successive Approximation Register (SAR) Analogue-to-Digital Converters (ADC)

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Analogue-to-digital conversion (ADC) for medium speed and medium resolution applications is often performed by capacitively successive approximation register (SAR) analogue-to-digital converters. They employ three core functions: charging capacitors, charge redistribution and voltage comparison. Each of them consumes battery power or burns power. The charge redistribution DAC, together with its control logic, is a major part of the total power consumption. Charging capacitors from a voltage source offers potential power savings depending on the wave form of the power source. In this project we combine optimum wave form design and new switching schemes to achieve minimal power consumption. Microelectronic implementation constraints, e.g. parasitics from layout are also taken into account for practically realizable switching schemes.For comparison of different solutions a new figure of merit (FoM) for the switching schemes will be defined to cover energy consumption, linearity and speed. A proof of concept in silicon concludes the project and will demonstrate the achieved energy savings.