Realization of a High-level Language Direct Execution Computer for Interactive Programming

为了实现面向过程语言的高度交互式程序设计环境，设计并建立了一个通用直接执行计算机（UDEC），它是一种无需编译就能直接执行源程序的体系结构。UDEC由一个语言处理器和一个交互处理器组成。语言处理器采用流水线结构，连接词法处理器、语法和语义识别器以及执行处理器。为了增加语言的独立性，解释语法已经被引入，语义动作被描述为与语言的产生式规则相结合。解释文法在词法处理器和语法语义识别器中尽可能地转换为表驱动的控制算法，尽管由于其复杂性，语义动作在微程序中编码。交互式处理器被实现为具有三个高分辨率显示终端的微型计算机，以实现与用户的高度交互式界面。为了评价和改进UDEC的直接执行算法和体系结构，已经实现了PASCAL子集的控制算法。实现了寄存器传输级模拟器和概要分析器，并对语言处理器的动态行为进行了详细的模拟分析。在VAXII/750 UNIX上执行几个示例程序进行了模拟。仿真结果表明，高速硬件栈、硬件关联搜索机制、地址计算机制以及功能模块级流水线结构是有效的。

A Universal Direct-Execution Computer(UDEC) has been designed and built as an architecture executing a source program directly without compilation, for the basis of the realization of a highly interactive programming environment of procedure oriented languages. The UDEC consists of a language processor and an interactive processor. The language processor incorporates a pipeline architecture connecting the lexical processor, the syntax and semantics recognizer, and execution processor. To increase language independence, an interpretation grammar has been introduced and semantic actions are described being combied with the production rules of the language. The interpretation grammar is then transformed into a table driven control algorithm as far as possible in the lexical processor and the syntax and semantics recognizer, although the semantic actions are coded in microprogram due to its complexity. The interactive processor is implemented as a microcomputer with three high resolution display terminals to realize a highly interactive interface with users. To evaluate and improve the direct-execution algorithm and the architecture of the UDEC, the control algorithm for a PASCAL subset has been implemented. A register transfer level simulator and a profile analyzer were also implemented, and detail simulation was done analyzing the dynamic behavior of the language processor. The simulation has been done on VAXII/750 UNIX executing several sample programs. The simulation results showed that high speed hardware stack, hardware associative search mechanism, and address calculation mechanism are strongly effective as well as the functional module level pipeline architecture.