Studies on Bloch Line Memory for Practical Use

Bloch 行存储器的实用研究

• 批准号: 62850069
• 负责人: MATSUYAMA Kimihide
• 金额: $ 8万
• 依托单位: Department of Electrical Engineering, Kyushu University
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for Developmental Scientific Research
• 财政年份: 1987
• 资助国家: 日本
• 起止时间: 1987 至 1989
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-62850069/
• 关键词: Magnetic Memory; Vertical Bloch Line; Magnetic Wall; Bubble Domain

In order to put a nobel solid state magnetic memory (Bloch line memory) to practical use, the following memory functions were confirmed in a test chip processed on a LPE garnet film for 10 Mbit/cm^2 Bloch line memory (nominal stripe width is 5 um). 1. VBL storage area of 1 mm^2 was constructed by parallel grooved patterns formed by the wet etching method using heated phosphoric acid. 2. A computer controlled chip tester was fabricated, and the simultaneous read and write operations for multiple stripe domains was confirmed by the chip tester. 3. Bit stabilization effect due to the stress induced anisotropy caused by periodically patterned Cr film was studied numerically. Bit propagation of VBLs was realized in a test chip, which was fabricated according to the design criteria obtained from the numerical results. 4. A new architecture of major line bubble propagation path having large misalignment tolerance was processed. A read-write gate with the bubble propagation path was processed … More on a test chip. Sequential gate operations, that is, conversion of bit informations from VBLs to bubbles, bubble propagation, bubble stretching, were confirmed on the chip.A read-write gate having reasonable operation margin was processed on a LPE garnet film for 40 Mbit/cm^2 Bloch line memory (nominal stripe width is 2 um) as a next step to increase the bit density. The temporal and spatial variations of the detailed micromagnetic structures during the wall merging process was studied numerically. It was found that the read operation error was caused by the dynamic wall structure change (nucleation of the horizontal Bloch line), and the operation condition to suppress it was clarified. Furthermore, An accurate mathematical formula for the effective wall-demagnetizing pressure was derived. The simulated result using the formula agreed well with the theory in the case of material with small characteristics factor (q=2.8), which would be used for Bloch line memory of more than 100 Mbit/cm^2. Less

为了将诺贝尔固态磁存储器（布洛赫线存储器）投入实际使用，在LPE石榴石膜上加工的测试芯片中确认了以下存储器功能，用于10 Mbit/cm^2布洛赫线存储器（标称条宽为5 μ m）。1. 1 mm^2的VBL存储区域通过使用加热磷酸的湿法蚀刻方法形成的平行沟槽图案来构造。2.研制了一台计算机控制的芯片测试机，并通过该测试机验证了多条畴的同时读写操作。3.数值研究了周期性图形化Cr膜引起的应力感生各向异性对比特稳定的影响。根据数值计算结果得到的设计准则制作了一个测试芯片，实现了VBL的比特传输。4.提出了一种具有较大失调容限的主线气泡传播路径结构。处理了具有气泡传播路径的读写门 ...更多信息 在测试芯片上。在该芯片上实现了位信息从VBL到Bubble的转换、Bubble的传播、Bubble的拉伸等顺序门操作，并在40 Mbit/cm^2 Bloch线存储器（标称条宽为2 μ m）的LPE石榴石薄膜上加工了具有合理操作裕度的读写门，以提高位密度。数值研究了壁合并过程中详细微磁结构的时空变化。发现读操作误差是由动态壁结构变化（水平布洛赫线的成核）引起的，并阐明了抑制它的操作条件。此外，还推导出了有效壁面去磁压力的精确数学公式。在材料特性因子较小（q=2.8）的情况下，用该公式模拟的结果与理论符合得很好，可用于大于100 Mbit/cm ^2的布洛赫线存储器。少

项目成果

T. Suzuki: "Initiating stripe domains in Bloch line memory" IEEE Trans. Magn., Vol.MAG-23, No.5, pp.3393-3395(1987).

T. Suzuki：“在 Bloch 行存储器中启动条带域” IEEE Trans。

S.Konishi: "Computer simulation for wall merging process in Bloch line read operation" IEEE Trans.Magn.,Vol.24. 6. 3036-3038 (1988)

S.Konishi：“Bloch 行读取操作中的墙合并过程的计算机模拟”IEEE Trans.Magn.，Vol.24。

Y. Nakatani: "Three-dimension calculation of vertical Bloch line and Bloch point" IEEE Trans. Magn., Vol.24, No.6, pp.3039-3041(1988).

Y. Nakatani：“垂直布洛赫线和布洛赫点的三维计算”IEEE Trans。

H. Kawahara: "Stable multi-domain generation and gate operation for Bloch line memory" IEEE Trans. Magn., Vol.24, No.6, pp.3030-3032(1988).

H. Kawahara：“Bloch 行存储器的稳定多域生成和门操作”IEEE Trans。

H.Kawahara: "A new method to stabilize multi-stripe domains for a Bloch line memory" IEEE Trans.Magn.,Vol.MAG-23. 5. 3396-3398 (1987)

H.Kawahara：“一种稳定 Bloch 线存储器多条带域的新方法”IEEE Trans.Magn.，Vol.MAG-23。