SCAD: Synchronous Control Asynchronous Dataflow (SCAD) Architectures

SCAD：同步控制异步数据流 (SCAD) 架构

• 批准号: 424386388
• 负责人: Professor Dr. Klaus Schneider
• 金额: --
• 依托单位: Arbeitsgruppe Eingebettete Systeme
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2020
• 资助国家: 德国
• 起止时间: 2019-12-31 至 2022-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/424386388?language=en
• 关键词: SCAD; Synchronous; Control; Asynchronous; Dataflow

Reactive embedded real-time systems are nowadays often developed by model-based design flows. In particular, synchronous models became popular, where a time-driven clock is used to trigger the reaction steps of the system. In every reaction step, the system reads its inputs and computes its outputs by executing the micro step actions scheduled in this macro step reaction. Typical design phases like simulation, formal verification, and other system analyses like the estimation of the worst case reaction time are simplified by the deterministic and formal semantics of synchronous models.However, the usual software synthesis of a synchronous model still generates a sequential program where the actually concurrent micro steps are scheduled in a causally correct sequential order. Processors executing these programs will therefore typically find a large amount of instruction-level parallelism (ILP) to increase their performance. However, the amount of ILP that can be exploited by current processor architectures like superscalar and VLIW processors is relatively low, and one particular reason for this is the use of registers. For this reason, `exposed datapath architectures' (EDPA) have been developed which allow the compilers to generate programs that control besides the internal instruction scheduling also the allocation of function units and the data transports without making use of traditional registers.In this project, we develop a new and innovative exposed datapath architecture called SCAD (synchronous control, asynchronous dataflow) that will be used to efficiently execute sequential programs with a high degree of ILP as the ones obtained from model-based design flows. A SCAD architecture consists of a number of possibly application-specific function units (FUs) whose inputs and outputs are (FIFO) buffered. SCAD programs consist of a sequence of move instructions that instruct the output buffers to send the computed results to input buffers of other function units. The move instructions are synchronously registered in the producer and consumer FUs to ensure the correct ordering of operands of each FU. However, the execution of the FUs will proceed in dataflow order and will therefore naturally exploit the contained ILP.In principle, the SCAD architecture is the result of previous research on hardware and software synthesis of synchronous programs: It improves previous approaches to hardware and sequential software synthesis and can even make effective use of application-specific FUs.In the research project, we intend to develop and to evaluate variants of the SCAD machine with different interconnection networks on FPGAs, will develop cycle-accurate simulators, and efficient compilers that should generate nearly optimal code. We moreover plan to consider optimizations like branch prediction and out-of-order execution as well as temporary coupling of FUs as a means for runtime reconfiguration.

反应式嵌入式实时系统目前通常采用基于模型的设计流程进行开发。特别是，同步模型变得流行起来，其中使用时间驱动的时钟来触发系统的反应步骤。在每个反应步骤中，系统通过执行在该宏观步骤反应中安排的微观步骤动作来读取其输入并计算其输出。同步模型的确定性和形式化语义简化了仿真、形式化验证等典型设计阶段和最坏情况反应时间估计等系统分析阶段，但通常的同步模型软件综合仍然生成顺序程序，其中实际并发的微步骤按因果关系正确的顺序进行调度。因此，执行这些程序的处理器通常会找到大量指令级并行性(ILP)来提高其性能。然而，当前的处理器体系结构(如超标量和VLIW处理器)可以利用的ILP数量相对较少，其中一个特殊原因是使用了寄存器。为此，我们开发了一种新的开放数据路径体系结构，它允许编译器在不使用传统寄存器的情况下，生成除了控制内部指令调度之外，还控制功能单元分配和数据传输的程序。在这个项目中，我们开发了一种新的创新的开放数据路径体系结构，称为SCAD(同步控制，异步数据流)，它将用于高效地执行具有高度ILP的顺序程序，而不是基于模型的设计流程。SCAD体系结构由许多可能特定于应用的功能单元(FU)组成，其输入和输出被(FIFO)缓冲。SCAD程序由一系列移动指令组成，这些指令指示输出缓冲区将计算结果发送到其他功能单元的输入缓冲区。移动指令被同步地登记在生产者和消费者FU中，以确保每个FU的操作数的正确排序。然而，FU的执行将按数据流顺序进行，因此将自然地利用所包含的IL.原则上，SCAD体系结构是先前对同步程序的硬件和软件综合的研究的结果：它改进了以前的硬件和顺序软件综合的方法，甚至可以有效地利用特定于应用的保险丝.在研究项目中，我们打算开发和评估具有不同互连网络的在现场可编程门阵列上的SCAD机器的变体，将开发周期精确的模拟器和高效的编译器，应该能够生成近乎最优的代码.此外，我们还计划考虑将分支预测和无序执行等优化以及FU的临时耦合作为运行时重新配置的一种手段。