SCAD: Synchronous Control Asynchronous Dataflow (SCAD) Architectures

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Reactive embedded real-time systems are nowadays often developed by model-based design flows. In particular, synchronous models became popular, where a time-driven clock is used to trigger the reaction steps of the system. In every reaction step, the system reads its inputs and computes its outputs by executing the micro step actions scheduled in this macro step reaction. Typical design phases like simulation, formal verification, and other system analyses like the estimation of the worst case reaction time are simplified by the deterministic and formal semantics of synchronous models.However, the usual software synthesis of a synchronous model still generates a sequential program where the actually concurrent micro steps are scheduled in a causally correct sequential order. Processors executing these programs will therefore typically find a large amount of instruction-level parallelism (ILP) to increase their performance. However, the amount of ILP that can be exploited by current processor architectures like superscalar and VLIW processors is relatively low, and one particular reason for this is the use of registers. For this reason, `exposed datapath architectures' (EDPA) have been developed which allow the compilers to generate programs that control besides the internal instruction scheduling also the allocation of function units and the data transports without making use of traditional registers.In this project, we develop a new and innovative exposed datapath architecture called SCAD (synchronous control, asynchronous dataflow) that will be used to efficiently execute sequential programs with a high degree of ILP as the ones obtained from model-based design flows. A SCAD architecture consists of a number of possibly application-specific function units (FUs) whose inputs and outputs are (FIFO) buffered. SCAD programs consist of a sequence of move instructions that instruct the output buffers to send the computed results to input buffers of other function units. The move instructions are synchronously registered in the producer and consumer FUs to ensure the correct ordering of operands of each FU. However, the execution of the FUs will proceed in dataflow order and will therefore naturally exploit the contained ILP.In principle, the SCAD architecture is the result of previous research on hardware and software synthesis of synchronous programs: It improves previous approaches to hardware and sequential software synthesis and can even make effective use of application-specific FUs.In the research project, we intend to develop and to evaluate variants of the SCAD machine with different interconnection networks on FPGAs, will develop cycle-accurate simulators, and efficient compilers that should generate nearly optimal code. We moreover plan to consider optimizations like branch prediction and out-of-order execution as well as temporary coupling of FUs as a means for runtime reconfiguration.