SCAD: Synchronous Control Asynchronous Dataflow (SCAD) Architectures

SCAD：同步控制异步数据流 (SCAD) 架构

• 批准号: 424386388
• 负责人: Professor Dr. Klaus Schneider
• 金额: --
• 依托单位: Arbeitsgruppe Eingebettete Systeme
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2020
• 资助国家: 德国
• 起止时间: 2019-12-31 至 2022-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/424386388?language=en
• 关键词: SCAD; Synchronous; Control; Asynchronous; Dataflow

Reactive embedded real-time systems are nowadays often developed by model-based design flows. In particular, synchronous models became popular, where a time-driven clock is used to trigger the reaction steps of the system. In every reaction step, the system reads its inputs and computes its outputs by executing the micro step actions scheduled in this macro step reaction. Typical design phases like simulation, formal verification, and other system analyses like the estimation of the worst case reaction time are simplified by the deterministic and formal semantics of synchronous models.However, the usual software synthesis of a synchronous model still generates a sequential program where the actually concurrent micro steps are scheduled in a causally correct sequential order. Processors executing these programs will therefore typically find a large amount of instruction-level parallelism (ILP) to increase their performance. However, the amount of ILP that can be exploited by current processor architectures like superscalar and VLIW processors is relatively low, and one particular reason for this is the use of registers. For this reason, `exposed datapath architectures' (EDPA) have been developed which allow the compilers to generate programs that control besides the internal instruction scheduling also the allocation of function units and the data transports without making use of traditional registers.In this project, we develop a new and innovative exposed datapath architecture called SCAD (synchronous control, asynchronous dataflow) that will be used to efficiently execute sequential programs with a high degree of ILP as the ones obtained from model-based design flows. A SCAD architecture consists of a number of possibly application-specific function units (FUs) whose inputs and outputs are (FIFO) buffered. SCAD programs consist of a sequence of move instructions that instruct the output buffers to send the computed results to input buffers of other function units. The move instructions are synchronously registered in the producer and consumer FUs to ensure the correct ordering of operands of each FU. However, the execution of the FUs will proceed in dataflow order and will therefore naturally exploit the contained ILP.In principle, the SCAD architecture is the result of previous research on hardware and software synthesis of synchronous programs: It improves previous approaches to hardware and sequential software synthesis and can even make effective use of application-specific FUs.In the research project, we intend to develop and to evaluate variants of the SCAD machine with different interconnection networks on FPGAs, will develop cycle-accurate simulators, and efficient compilers that should generate nearly optimal code. We moreover plan to consider optimizations like branch prediction and out-of-order execution as well as temporary coupling of FUs as a means for runtime reconfiguration.

反应式嵌入式实时系统目前通常采用基于模型的设计流程。特别是，同步模型变得流行，其中时间驱动的时钟用于触发系统的反应步骤。在每个反应步骤中，系统读取其输入并通过执行在该宏步骤反应中调度的微步骤动作来计算其输出。典型的设计阶段，如仿真，形式验证，和其他系统分析，如最坏情况下的反应时间的估计，简化了同步模型的确定性和形式语义，然而，通常的同步模型的软件综合仍然会产生一个顺序的程序，实际上并发的微步骤被安排在一个因果关系正确的顺序。因此，执行这些程序的处理器通常会找到大量的并行级并行（ILP）来提高其性能。然而，当前处理器架构（如超标量和VLIW处理器）可以利用的ILP数量相对较低，一个特殊的原因是使用寄存器。基于此，“暴露式数据路径体系结构”（EDPA）被提出，它允许编译器在不使用传统寄存器的情况下，生成控制内部指令调度以及功能单元分配和数据传输的程序。在本项目中，我们开发了一种新的和创新的暴露式数据路径体系结构SCAD（同步控制，异步异步控制），其将用于以高度的ILP有效地执行顺序程序，如从基于模型的设计流程获得的程序。SCAD架构由许多可能特定于应用的功能单元（FU）组成，其输入和输出经过（FIFO）缓冲。SCAD程序由一系列移动指令组成，这些指令指示输出缓冲器将计算结果发送到其他功能单元的输入缓冲器。移动指令被同步地注册在生产者FU和消费者FU中，以确保每个FU的操作数的正确排序。然而，FU的执行将以较低的顺序进行，因此将自然地利用所包含的ILP。原则上，SCAD体系结构是先前对同步程序的硬件和软件合成的研究的结果：它改进了以前的硬件和顺序软件综合方法，甚至可以有效地利用特定于应用的FU。我们打算在FPGA上开发和评估具有不同互连网络的SCAD机器的变体，将开发周期精确的模拟器和高效的编译器，这些编译器将生成接近最佳的代码。此外，我们计划考虑优化，如分支预测和乱序执行，以及作为运行时重新配置的手段的FU的临时耦合。