SCAD: Synchronous Control Asynchronous Dataflow (SCAD) Architectures

SCAD：同步控制异步数据流 (SCAD) 架构

• 批准号: 424386388
• 负责人: Professor Dr. Klaus Schneider
• 金额: --
• 依托单位: Arbeitsgruppe Eingebettete Systeme
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2020
• 资助国家: 德国
• 起止时间: 2019-12-31 至 2022-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/424386388?language=en
• 关键词: SCAD; Synchronous; Control; Asynchronous; Dataflow

Reactive embedded real-time systems are nowadays often developed by model-based design flows. In particular, synchronous models became popular, where a time-driven clock is used to trigger the reaction steps of the system. In every reaction step, the system reads its inputs and computes its outputs by executing the micro step actions scheduled in this macro step reaction. Typical design phases like simulation, formal verification, and other system analyses like the estimation of the worst case reaction time are simplified by the deterministic and formal semantics of synchronous models.However, the usual software synthesis of a synchronous model still generates a sequential program where the actually concurrent micro steps are scheduled in a causally correct sequential order. Processors executing these programs will therefore typically find a large amount of instruction-level parallelism (ILP) to increase their performance. However, the amount of ILP that can be exploited by current processor architectures like superscalar and VLIW processors is relatively low, and one particular reason for this is the use of registers. For this reason, `exposed datapath architectures' (EDPA) have been developed which allow the compilers to generate programs that control besides the internal instruction scheduling also the allocation of function units and the data transports without making use of traditional registers.In this project, we develop a new and innovative exposed datapath architecture called SCAD (synchronous control, asynchronous dataflow) that will be used to efficiently execute sequential programs with a high degree of ILP as the ones obtained from model-based design flows. A SCAD architecture consists of a number of possibly application-specific function units (FUs) whose inputs and outputs are (FIFO) buffered. SCAD programs consist of a sequence of move instructions that instruct the output buffers to send the computed results to input buffers of other function units. The move instructions are synchronously registered in the producer and consumer FUs to ensure the correct ordering of operands of each FU. However, the execution of the FUs will proceed in dataflow order and will therefore naturally exploit the contained ILP.In principle, the SCAD architecture is the result of previous research on hardware and software synthesis of synchronous programs: It improves previous approaches to hardware and sequential software synthesis and can even make effective use of application-specific FUs.In the research project, we intend to develop and to evaluate variants of the SCAD machine with different interconnection networks on FPGAs, will develop cycle-accurate simulators, and efficient compilers that should generate nearly optimal code. We moreover plan to consider optimizations like branch prediction and out-of-order execution as well as temporary coupling of FUs as a means for runtime reconfiguration.

如今，反应性嵌入式实时系统通常是由基于模型的设计流而开发的。特别是，同步模型变得流行，在该模型中使用时驱动时钟来触发系统的反应步骤。在每个反应步骤中，系统都通过在此宏步骤反应中执行安排的微观步骤操作来读取其输入并计算其输出。 Typical design phases like simulation, formal verification, and other system analyses like the estimation of the worst case reaction time are simplified by the deterministic and formal semantics of synchronous models.However, the usual software synthesis of a synchronous model still generates a sequential program where the actually concurrent micro steps are scheduled in a causally correct sequential order.因此，执行这些程序的处理器通常会找到大量的指令级并行性（ILP）以提高其性能。但是，当前处理器架构（如SuperScalar和VLIW处理器）可以利用的ILP数量相对较低，而这是一个特殊原因是使用寄存器。 For this reason, `exposed datapath architectures' (EDPA) have been developed which allow the compilers to generate programs that control besides the internal instruction scheduling also the allocation of function units and the data transports without making use of traditional registers.In this project, we develop a new and innovative exposed datapath architecture called SCAD (synchronous control, asynchronous dataflow) that will be used to efficiently execute sequential programs with a高度的ILP作为从基于模型的设计流中获得的ILP。 SCAD架构由许多可能的特定应用功能单元（FUS）组成，其输入和输出为（FIFO）缓冲。 SCAD程序由一系列移动指令组成，该指令指示输出缓冲区将计算结果发送到其他功能单元的输入缓冲区。移动说明是在生产者和消费者FUS中同步注册的，以确保每个FU操作数的正确订购。但是，FUS的执行将以数据流顺序进行，因此自然会利用所包含的ILP。原则上，SCAD体系结构是先前关于同步程序硬件和软件合成的研究的结果：它可以改善硬件和顺序软件合成的先前方法，甚至可以与应用程序的有效使用，我们可以在Scepific fip.in中进行有效使用。 FPGAS上的网络将开发自行车精确的模拟器，以及应生成几乎最佳代码的有效编译器。此外，我们计划考虑优化分支预测和排序执行以及FUS的临时耦合，以作为运行时重新配置的一种手段。