Verification and synthesis of structural features of analog/mixed-signal circuit using constraint programming exampled by ESD and level shifting

使用以 ESD 和电平移位为例的约束编程验证和综合模拟/混合信号电路的结构特征

• 批准号: 431736995
• 负责人: Professor Dr.-Ing. Helmut Gräb
• 金额: --
• 依托单位: Lehrstuhl für Entwurfsautomatisierung (EDA)
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2020
• 资助国家: 德国
• 起止时间: 2019-12-31 至 2022-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/431736995?language=en
• 关键词: Verification; synthesis; structural; features; analog

Goal of the project are new methods for the automated verification of the circuit parts required for ESD and level-shift of analog/mixed-signal components in integrated system. In particular, the correctness of the overall circuit, i.e., whether the correct additional components have been inserted in the right places in the netlist in the manual design. The development of the methods involves penetrating and systematizing the underlying circuitry design principles, the formulation and subsequent software implementation of an automated design process, and validation using practical circuits.Another goal of the project is to create an automated synthesis of the circuit parts required for ESD and level-shift of analog/mixed-signal components in the system based on the developed systematic rules for the verification. This includes the conversion of verification rules into declarative conditions of numerical, logical or integer kind, which serve as the basis of optimization procedures. Design knowledge should be formulated as far as possible in the form of constraints and optimization goals in order to limit the solution space so much that the developer has only to select from a few essential alternative solutions.An essential mathematical means for solving both goals will be constraint programming.As a third goal, the project aims to obtain hints and suggestions for the structural synthesis of analog/mixed-signal circuits with regard to the primary properties such as gain, bandwidth, phase margin, slew rate.

该项目的目标是为ESD所需的电路部件的自动验证和集成系统中模拟/混合信号元件的电平漂移提供新的方法。尤其是整个电路的正确性，即在手动设计中是否在网表中的正确位置插入了正确的附加元件。该方法的开发包括深入和系统化基本电路设计原则，自动设计过程的制定和后续软件实施，以及使用实际电路进行验证。该项目的另一个目标是根据为验证制定的系统规则，创建系统中ESD所需的电路部件和模拟/混合信号部件的电平漂移的自动综合。这包括将核查规则转换为数字、逻辑或整型的声明性条件，作为优化程序的基础。设计知识应尽可能地以约束和优化目标的形式表达，以限制解空间，使得开发人员只需从几个基本备选解决方案中进行选择。解决这两个目标的基本数学方法将是约束编程。作为第三个目标，该项目旨在获得关于诸如增益、带宽、相位裕度、转换速率等基本特性的关于模拟/混合信号电路的结构综合的提示和建议。