Verification and synthesis of structural features of analog/mixed-signal circuit using constraint programming exampled by ESD and level shifting

点击翻译按钮获取中文摘要

Goal of the project are new methods for the automated verification of the circuit parts required for ESD and level-shift of analog/mixed-signal components in integrated system. In particular, the correctness of the overall circuit, i.e., whether the correct additional components have been inserted in the right places in the netlist in the manual design. The development of the methods involves penetrating and systematizing the underlying circuitry design principles, the formulation and subsequent software implementation of an automated design process, and validation using practical circuits.Another goal of the project is to create an automated synthesis of the circuit parts required for ESD and level-shift of analog/mixed-signal components in the system based on the developed systematic rules for the verification. This includes the conversion of verification rules into declarative conditions of numerical, logical or integer kind, which serve as the basis of optimization procedures. Design knowledge should be formulated as far as possible in the form of constraints and optimization goals in order to limit the solution space so much that the developer has only to select from a few essential alternative solutions.An essential mathematical means for solving both goals will be constraint programming.As a third goal, the project aims to obtain hints and suggestions for the structural synthesis of analog/mixed-signal circuits with regard to the primary properties such as gain, bandwidth, phase margin, slew rate.