Research on Formal Verification of Finite State Systems
Research on Formal Verification of Finite State Systems
批准号:
05680285
负责人:
HIRAISHI Hiromi
金额:
$1.34万
依托单位:
依托单位国家:
日本
项目类别:
Grant-in-Aid for General Scientific Research (C)
财政年份:
1993
资助国家:
日本
项目状态:
已结题
起止时间:
1993 至 1994
中文摘要
为了建立实际规模有限状态系统的基本形式化验证方法,本文主要研究了基于时态逻辑符号模型检测的形式化设计验证。1.符号模型检测算法:由于逆图像计算是时态逻辑符号模型检测的基本运算之一,本文提出了一种新的高效的逆图像计算算法。将该算法应用于8位微处理器的验证,结果表明,与传统的逆图像计算算法相比,新算法的速度提高了约60倍。2.时空模式逻辑:针对位片结构的验证,提出了一种新的转换系统,它有两种转换类型:一种用于时间转换,另一种用于空间转换。该转换系统可以作为位片电路的模型。对于转换系统的描述语言,提出了时空模态逻辑,并给出了其符号模型检验算法。3.实时系统的验证:对于实时系统验证的基本算法,提出了几种符号算法。通过使用这些算法,我们可以得到两类事件之间的时间上界和下界,以及给定时间段内事件发生的上界和下界。这些都是实时系统的基本特征,它们的计算在实时系统的验证中是非常重要的。4.16位微处理器的形式化验证:为了使16位微处理器的验证成为可能,研究了各种抽象方法。其中,数据宽度提取到8位和信号固定是非常有效的。通过这两种方法的结合,我们成功地验证了16位微处理器。
英文摘要
Aiming at establishment of fundamental formal verification methodology for finite state systems of practical size, I mainly investigated formal design verification based on symbolic model checking of temporal logic. The major results of this research are summarized below :1.Symbolic Model Checking Algorithm : Since an inverse image computation is one of the basic operations in symbolic model checking of temporal logic, I proposed an efficient new inverse image computation algorithm. The proposed algorithm was applied to a verification of 8 bit microprocessor, and the result showed that the new algorithm achieved around 60 times speed-up compared with conventional inverse image computation algorithms.2.Time-Space Modal Logic : Aiming at verification of bit-slice architecture, I proposed a new transition system that has tow types of transition ; one for time transitions and the others for space transitions. The transition system cab be used as a model of a bit-slice circuits. As for a specification language on the transition system, I proposed time-space modal logic and showed its symbolic model checking algorithm.3.Verification of Real-Time Systems : As for basic algorithms in verification of real-time systems, a couple of symbolic algorithms have been proposed. By using these algorithms, we can obtain upper bound and lower bound of time between two types of events and upper bound and lower bound of event occurrences in a given time period. These are basic characteristics of real-time systems and calculations of them are important in verification of real-time systems.4.Formal Verification of 16 bit microprocessor : Various abstract methods were investigated to make verification of 16 bit microprocessor possible. Among them, abstraction of data width to 8 bit and signal fixing were very effective. By combining these two methods, we succeeded to verify 16 bit microprocessor.
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H.Hiraishi: "An Efficient Inverse Image Computation Algorithm for Sequential Machine Verification Using Temporal Logics" Computer Systems Science & Engineering. Vol.9. 112-117 (1994)
H.Hiraishi:“使用时间逻辑进行顺序机器验证的高效逆图像计算算法”计算机系统科学
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H.Hiraishi: "Formal Verification of Single Phase Behavior of KUECHIP2 Microprocessor" New Advances in Computer Aided Design & Computer Graphics. Vol.II. 611-616 (1993)
H.Hiraishi:“KUECHIP2微处理器单相行为的形式验证”计算机辅助设计新进展
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平石裕実: "論理関数処理に基づく形式的検証手法" 情報処理. 35. 710-718 (1994)
Hiromi Hiraishi:“基于逻辑函数处理的形式验证方法”信息处理35。710-718(1994)。
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S.V.Campos: "Computing Quantitative Characteristics of Finite-State Real-Time Systems" Proc.Real-Time System Symp.266-270 (1994)
S.V.Campos:“计算有限状态实时系统的定量特征”Proc.Real-Time System Symp.266-270 (1994)
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平石裕実: "An Efficient Inverse Image Computation Algorithm for Seguenfial Machine Verificafion" Proc.PRFTS'93. 91-95 (1993)
Hiromi Hiraishi:“一种用于连续机器验证的高效逆图像计算算法”Proc.PRFTS93 (1993)。
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共 16 条
Parallel Logic Design Verification Based on Module Dependence
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批准号:18500043
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.29万
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财政年份:2006
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负责人:HIRAISHI Hiromi
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依托单位:
Parallel and Distributed Formal Logic Design Verification for Workstation Cluster System
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批准号:12680361
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.24万
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财政年份:2000
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负责人:HIRAISHI Hiromi
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依托单位:
Studies on Formal Logic Design Verification
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批准号:09680348
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项目类别:Grant-in-Aid for Scientific Research (C)
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资助金额:$2.37万
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财政年份:1997
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负责人:HIRAISHI Hiromi
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依托单位:
Research on Computer Aided Formal Verification Based on Temporal Logics
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批准号:03650301
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项目类别:Grant-in-Aid for General Scientific Research (C)
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资助金额:$1.79万
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财政年份:1991
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负责人:HIRAISHI Hiromi
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依托单位:
Researches on Formal Logic Design Verification Based on Regular Temporal Logic
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批准号:01550285
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项目类别:Grant-in-Aid for General Scientific Research (C)
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资助金额:$1.47万
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财政年份:1989
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负责人:HIRAISHI Hiromi
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依托单位:
海外基金